When a finished-thickness callout gets pushed back in engineering review, the conversation almost always starts in the wrong place. The drawing says a thickness, the fab says it cannot build it, and the designer's first move is to ask whether the tolerance can be opened up.
Opening the tolerance does not fix this class of problem, because two unrelated questions are being asked at once:
- Question A: what tolerance governs the thickness I wrote?
- Question B: can a stackup actually be arranged that lands on the thickness I wrote?
Question A has a published answer. On /en/tolerance/ the thickness tolerance is ±10% or ±0.005" (≈0.13 mm), whichever is greater. How that rule takes effect, how it is measured, how the board is released against it, and when it is worth paying to tighten it are covered in finished PCB thickness tolerance control. This article does not repeat any of it.
This article is only about Question B, and the answer has nothing to do with tolerance: buildable finished thickness is not a continuous range, it is a set of points. SKPCB publishes a thickness range of 0.2–6.0 mm (6.0 mm maximum, see /en/capabilities/), but that is a span of support, not a promise that every decimal inside it can be built. What can be built are the values that happen to be summable from available cores, prepreg and copper weights. Write a value that cannot be summed, and no tolerance width will produce a stackup centered on it.
The buildup ledger: what actually adds up to a finished thickness
Break the finished thickness into line items and Question B stops being mysterious. For a multilayer board there are five classes of contribution.
One: inner-layer cores. A core is a double-sided laminate that arrives already cured. Its dielectric thickness and both base copper weights were fixed at purchase. An N-layer board contains some number of cores, each contributing a fixed value. Core thicknesses exist only in finite steps — this is the least negotiable item in the whole ledger, because it comes from the laminate supplier's standard offering, not from anything adjustable at lamination.
Two: prepreg between layers. Prepreg resin flows and compacts during lamination, so pressed thickness is less than the pre-press nominal, and how much less depends on the copper distribution of the adjacent layers and on press conditions. This is the only item in the ledger with any continuity to it: changing the count and type of prepreg sheets per layer pair moves total thickness up or down a little. But its adjustment step is discrete too — you add or remove *a sheet*, not an arbitrary fraction. Specific thickness steps and pressed-down values are confirmed by engineering review against the actual stackup and are not quoted here.
Three: copper. Inner-layer copper comes from the core's base copper; outer-layer copper is base copper plus the buildup from hole metallization and pattern plating. Copper weights are themselves discrete steps (the published range is 0.5 oz to >12 oz, where >12 oz sits at the engineering-review tier and 16/18 oz has been produced). Selection rules for copper weight are in PCB copper thickness options and design rules; here copper is just a ledger line: thicker outer copper means a larger plating contribution and a higher total.
Four: soldermask. Mask covers outer copper and exposed substrate and contributes a thin but non-zero amount. Note how this interacts with the published rule: the minimum-thickness wording on /en/tolerance/ is stated including soldermask, which means the ledger ends at a *masked finished board*, not at the bare panel coming out of the press.
Five: surface finish. Different finishes leave different metal thicknesses on the pads and contribute differently to the total. It is usually the smallest line item, but on a thin board it cannot be treated as zero.
Those five sum to the finished thickness. Notice that none of the line items is the finished thickness itself — it is only their sum. That is exactly why specifying a finished thickness without constraining the stackup hands the fab an equation it has to solve on your behalf.
Why cores and prepreg turn buildable thickness into a discrete lattice
Now combine the discreteness of the line items. Core thickness comes in steps, prepreg adjusts by whole sheets, copper comes in steps — so the sum can only land on a finite number of points.
That set of points is the lattice of buildable nominal thicknesses, and its shape determines three practical things.
The lattice is not evenly spaced. In some thickness bands the available material steps are dense and adjacent buildable points sit very close together. In other bands the steps are sparse and there are visible jumps between neighbors. So a request like "make it a bit thicker than X" is sometimes almost free and sometimes forces a complete re-layup.
More layers means a coarser lattice. Adding layers adds line items, and every added item brings its own step constraint, so the number of feasible combinations goes down rather than up. Layer count is an input to this article rather than its subject; for what starts to bind when layer count itself is pushed high, see today's companion article on high-layer-count manufacturing constraints and the multilayer PCB stackup guide.
Missing the lattice does not get you a slightly out-of-spec board, it gets you an engineering query. This is the part worth remembering. If the drawing nominal falls between two buildable points, the fab has two options: build the nearer point (so nominal and actual center no longer coincide and part of the tolerance window is spent for nothing), or come back and ask which input you want changed. The second is the correct behavior, and it costs schedule.
How layer count and copper weight shift the whole lattice
The lattice is not fixed. It moves with two inputs.
Layer count moves its position and density. Each added inner-layer pair means another core and another prepreg layer, which raises the floor of achievable total thickness. The same finished thickness is therefore a completely different problem at different layer counts: comfortable at low counts, possibly already near the floor at high counts — at which point prepreg has been reduced to its minimum and further thinning has to come out of core selection.
Copper weight shifts the offset and changes prepreg demand. Heavy copper does more than enlarge the copper line item. The thicker the copper, the larger the steps between copper features that resin has to fill, and adequate fill and insulation often call for more or thicker prepreg — so copper weight affects total thickness by more than the copper itself. Heavy-copper capability limits are on /en/products/thick-copper-pcb/.
Both inputs have to be settled before thickness. That is the one ordering rule this article asks for: fix layer count and copper weight, see where the lattice lands, then pick a nominal from those points. Doing it the other way around — choosing a tidy finished thickness first and then trying to fit layers and copper to it — runs into the lattice almost every time.
Both ends of the range: what binds first on very thin and very thick boards
The lattice behaves differently at each end, and a different line item binds.
Thin end, near the 0.2 mm floor. What limits you here is not the press; it is stiffness and handleability, plus the fact that soldermask and surface finish are no longer negligible. A thin panel is clamped, conveyed and cleaned many times after lamination, and the thinner it is, the more warpage and distortion drive downstream yield loss (control measures are in multilayer copper balance and warpage control). The thin end also has a consequence that is easy to miss: because the rule is "±10% or ±0.005", whichever is greater," on thin boards the governing term is usually the ±0.005" absolute value rather than the percentage — meaning the relative tolerance on a thin board is in fact looser. That is the structure of the published rule, not a concession; details stay with finished PCB thickness tolerance control.
Thick end, near the 6.0 mm ceiling. Here the binding constraint is usually drilling, not pressing. The thicker the board, the higher the aspect ratio for a given hole diameter, and SKPCB's standard maximum aspect ratio is 10:1 (PCB-AR, standard tier). Thick boards and small holes are therefore not simultaneously free: once thickness is fixed, the floor on minimum buildable hole diameter follows from aspect ratio, and the standard mechanical minimum hole is 0.2 mm (0.15 mm sits at the engineering-review tier). The second thick-end constraint comes from copper and fill — heavy copper on a thick board needs more prepreg, pushing the total further up and easily hitting the ceiling.
What both ends share: closer to a boundary, the lattice is sparser, fewer nominals are available, and there is less room to "adjust slightly." If a design already sits against a boundary, state thickness as an acceptable range at RFQ and let engineering return the landing point, rather than publishing an exact nominal and getting it bounced.
Coupling: fixing thickness rewrites your aspect ratio, hole floor and impedance margin at the same time
Thickness is not an independent specification. It locks three other things.
Aspect ratio and minimum hole. As above, thickness divided by minimum hole diameter cannot exceed the standard 10:1. Fix the thickness and the hole floor is fixed; conversely, small holes require either a thinner board or the engineering-review tier (laser minimum hole 0.1 mm standard, 0.075 mm on review).
Impedance. Impedance is set jointly by trace width, copper thickness, dielectric thickness and dielectric constant — and dielectric thickness is precisely the prepreg and core lines of the ledger. Once total thickness is locked, freedom to adjust dielectric thickness is squeezed: bringing a differential pair onto its target impedance would normally mean swapping a prepreg step, and now that swap breaks the total. Impedance tolerance is ±10% (standard) / ±5% (engineering review); the classes and their tradeoffs are in impedance control PCB tolerance classes. The practical implication: on boards with tight impedance requirements, state total thickness as a range rather than a fixed value, or the two constraints will strangle each other.
Lamination and registration. Changing prepreg sheet counts changes resin flow and interlayer slip at lamination, and registration margin moves with it. This article does not open up press parameters; control measures are in multilayer lamination registration control.
These three couplings are why a fab receiving a "thickness only" change request asks to re-review the entire stackup. Thickness is not a field that can be edited on its own.
Giving a nominal thickness that exists: four things to submit before quoting
Collapsing all of the above into something actionable — before RFQ or engineering review, the design side should submit these four things rather than a thickness number.
- Layer count and layer function assignment. How many layers, and which are planes. This sets the position and density of the lattice.
- Inner and outer copper weight requirements, stated separately, along with whether current-carrying or thermal needs are driving heavy copper. Heavy copper raises both the copper line and the prepreg line.
- The form of the thickness requirement — fixed value or range — and why it is that value. If the thickness comes from a connector, a press-fit part, a card slot or an enclosure fit, stating that fit constraint is far more useful than stating a number: engineering can then pick the nearest buildable lattice point and tell you whether the fit still holds. If the thickness is only inherited habit, give a range.
- The other hard constraints that coexist with thickness: minimum hole diameter, impedance requirements, surface finish. All three couple to thickness, and supplying them together is what allows a feasible stackup to be arranged in one pass. Supplying them in installments causes repeated re-layup.
Submit those four and the output of engineering review is a specific stackup plus a nominal thickness that sits on the lattice, instead of another round trip about tolerance. What to check when releasing the stackup is in the multilayer stackup drawing release checklist. Capability limits and the material range are on /en/capabilities/ and /en/products/multi-layer-pcb/; to have us return the landing point directly, submit through /en/quote/.
FAQ
Q1: Why does the fab say my 1.55 mm cannot be built when 1.6 mm can?
Because buildable thickness is a set of points summed from available cores, prepreg and copper weights, not a continuous range. Two nominals a hair apart can fall on opposite sides of that distinction: one lands on a lattice point, the other between two of them. The fab then either builds the nearer point (nominal no longer coincides with actual center, spending part of the tolerance window for nothing) or returns a query asking which input to change. Actual landing points are confirmed by engineering review against real material availability.
Q2: Will opening up the thickness tolerance solve a "cannot build this thickness" problem?
Usually not. Tolerance governs how a finished board is judged; the lattice governs whether a stackup can be arranged at all. If the nominal sits off-lattice, a wider tolerance only makes an off-center result easier to accept — it does not make that nominal buildable. The governing rule itself is ±10% or ±0.005", whichever is greater; see finished PCB thickness tolerance control.
Q3: What does the published 0.2–6.0 mm mean? Can any thickness in that span be built?
It is the supported range with its bounds (6.0 mm maximum, see /en/capabilities/), not a claim of continuous selection inside it. A usable value must additionally be summable at your layer count and copper weight, and at the thick end must respect the aspect-ratio limit (standard maximum 10:1).
Q4: I only want the board a little thinner. Why does the whole stackup have to be re-reviewed?
Because thickness is the sum of five classes of contribution, so thinning has to be taken out of one of them: fewer prepreg sheets (changing lamination and registration conditions), a thinner core (changing dielectric thickness and therefore impedance), or less copper (changing current-carrying and thermal behavior). Each pulls on other specifications, which is why thickness is not independently editable.
Q5: Does "including soldermask" in the thickness tolerance matter?
Yes. The minimum-thickness wording on /en/tolerance/ is stated including soldermask, meaning the ledger runs through to a masked finished board rather than the bare laminated panel. On thin boards the mask and finish contributions are a non-trivial share, so budgeting against a bare panel comes out systematically low.
Q6: How should thickness be specified on a board with tight impedance requirements?
As an acceptable range, stated together with the impedance targets. Impedance depends on dielectric thickness, and dielectric thickness is the dominant line in the thickness ledger; if total thickness is pinned to a fixed value, the material swap needed to tune impedance breaks the total and the two constraints strangle each other. Impedance tolerance is ±10% (standard) / ±5% (engineering review) — see impedance control PCB tolerance classes.
Q7: Why does a thick board limit minimum hole size?
Aspect ratio = thickness ÷ hole diameter, and SKPCB's standard maximum aspect ratio is 10:1. Once thickness is set, that constraint directly implies a floor on buildable hole diameter; the standard mechanical minimum hole is 0.2 mm and the standard laser minimum hole is 0.1 mm, with smaller values at the engineering-review tier. Thick boards and small holes do not hold unconditionally at the same time.