Misregistration is not one event, it is a sum
When a microsection shows an inner-layer annular ring that is fat on one side and thin on the other, the usual conclusion is that the lamination press was misaligned. Lamination is only the last stretch of the chain. Between inner-layer imaging and drilling, an eight-layer board passes through etching, oxide treatment, lay-up, heat and pressure, cooldown, X-ray target location and drilling. Every one of those steps adds a small offset between where the inner-layer pattern actually is and where the hole ends up. What the microsection shows is the sum, not any single machine's readout.
The design consequence is blunt: misregistration cannot be solved by asking the fabricator to aim better, only by absorbing it with clearance. Clearance lives on the drawing, which makes it a design decision. If the clearance is not there, a perfectly aligned press still produces breakout. So this article does not discuss press parameters — that is process-side territory, and not something we would put numbers to here. It covers two things only: which steps actually generate the offset, and how much room you can give the chain on your drawing.
Even the reject criteria come from a standard rather than from judgement. Minimum annular ring, minimum hole-to-copper on inner layers and whether breakout is acceptable are graded by IPC-6012 Class 2 versus Class 3; visual defects are judged to IPC-A-600. Name the class on the drawing at design time. Class 2 and Class 3 tolerate very different ring conditions, and if you leave it unstated the fabricator can only release to their default — which turns into a dispute once the microsection report lands. SKPCB's multilayer build and acceptance framing is on the multilayer PCB page and the quality page.
The accumulation chain: four steps that actually contribute
Stage one, material movement. Inner-layer cores change dimension after etch and bake, and not uniformly — glass weave has different stiffness along warp and fill, so X and Y rarely move by the same amount on the same panel. The more layers you add and the more asymmetric the inner-layer copper distribution, the more visible that difference becomes. Fabricators pre-compensate with artwork scaling, but scaling is derived from batch statistics and cannot land at exactly zero on every panel. No scaling factor appears in this article. That value shifts with material lot, construction and copper distribution; it is process data, not a constant to publish.
Stage two, lay-up and movement under press. Lay-up stacks cores, prepreg and foil in sequence before pressing. Under heat and pressure the resin flows, and while it flows there is an opportunity for layers to move relative to one another. Riveting, pinning and mass-lam fusion exist to constrain that movement. Constraining is not eliminating.
Stage three, X-ray targeting and drill datum creation. A pressed panel is opaque; the drill cannot see the inner layers. So X-ray locates the buried targets, tooling holes are drilled from that reading, and all subsequent drilling references those holes. This step is the only channel that translates "where the inner layers actually are" into "where the drill goes" — and it is the one place design can exert influence. Whether there are enough targets, where they sit, and whether nearby copper interferes with them is decided by your inner-layer design.
Stage four, drilling's own position tolerance. Even with a correct datum, drilling carries its own positional error. The figure published on SKPCB's tolerance page is hole location ±0.003" (about 0.076 mm). Read that as drilling relative to the datum. It stacks with the first three stages; it does not replace them.
Those four together explain the familiar outcome where every individual step reports in-tolerance and the annular ring still comes up short. The design-side answer is not to interrogate each stage, but to accept that the sum exists and put extra room where it matters most.
How to actually use the two tolerances
Two numbers carry most of the design decisions.
First: inner-layer hole-to-copper = drill size + 0.020" (about 0.51 mm). This is the one to memorise. It means any inner-layer copper that must *not* connect to a given hole — an adjacent trace, a plane, another net's pad — has to sit far enough from the hole centre to leave roughly 0.010" of clearance on each side of the drill diameter. That clearance is not for the drill bit. It is for the whole error chain. Push inner-layer copper 5 mil closer and the drill can stay comfortably inside its own ±0.003" while still cutting into copper it was never supposed to touch.
Now invert it: inner-layer pads that must connect need annular ring reasoned the same way. An inner-layer pad only marginally larger than the drill will break out once the chain sums up. Inner-layer pads on multilayers usually need to be more generous than outer-layer pads, and this is why. Outer layers are imaged after lamination, so their relationship to the hole is a much shorter chain. Inner layers are imaged before lamination and carry the full chain.
Second: hole location ±0.003". Treat it as one line item in the error budget, not as the budget. When you check annular ring, consider it together with the inner-layer clearance requirement rather than reading it as total layer shift.
Both of these, plus board thickness ±10% or ±0.005" (whichever is greater), trace width ±20%, copper-to-copper spacing ±20%, outline ±0.005" and solder mask registration ±0.003", are the standard figures on the tolerance page. Anything tighter belongs to the advanced tier and requires item-by-item engineering review. Do not assume at design time that you will get it.
What to put on the drawing so misregistration is caught before build
This is the actionable part. Every item below belongs in the stackup drawing or fabrication notes, not in a comment buried in the design file.
- An explicit datum system. Give a primary and secondary datum, and reference hole location, outline and inner-layer imaging to the same set. Scatter datums across different features and the fabricator has to guess which one wins.
- Inner-layer target position and count. Put targets in the border outside the usable area, keep the four corners as symmetric as you can, and do not let large planes or dense patterns crowd them out. Trimmed or obscured targets leave the X-ray fitting from fewer points, and registration accuracy drops directly.
- A complete stackup table with per-layer copper weight and dielectric callouts. State copper and dielectric on every layer, and state the symmetry requirement. Asymmetric copper distribution amplifies dimensional differences, and the fabricator needs to know in advance.
- Acceptance class on the drawing. State IPC-6012 Class 2 or Class 3, and where the inner-layer annular ring criterion comes from.
- Which holes are critical. If some holes tolerate almost no inner-layer offset — dense vias in high-layer-count regions, for example — call them out so panelisation and compensation can treat them differently.
- List anything beyond the standard tier separately. Layer count above 40 (up to 64 sits in the high-layer-count and HDI range), mechanical holes below 0.2 mm, laser holes below 0.1 mm, aspect ratio beyond 10:1, impedance at ±5% — write each as "subject to engineering review." See the capabilities page.
How the fabricator proves registration was controlled
You provided clearance; the fabricator owes evidence. Three verifiable methods: microsection analysis — cut through critical holes and measure inner-layer annular ring and hole-to-copper directly, which is the only direct evidence of layer shift; post-lamination registration measurement — X-ray recheck of targets against tooling holes; and finished appearance and hole-wall inspection — visual defects judged to IPC-A-600. The pass criterion is still the class named on your drawing.
Material choice also moves the stability of this chain: dimensional stability differs between base materials, and prepreg resin content and flow act on both dimensional movement and interlayer displacement. Available systems are listed on the materials page. Mixed heavy-copper multilayers need extra thought about how copper distribution affects dimensional movement — see the heavy copper PCB page. To have engineering sanity-check a finished drawing before you commit, use the quote and engineering review entry.
FAQ
Q: Can misregistration be fixed by specifying a higher acceptance class?
No. The acceptance class decides what counts as conforming; it does not change the error chain. Class 3 screens out more panels, but if the drawing never had enough clearance the result is lower yield, not less misregistration. Clearance has to exist in the design first.
Q: How much larger should inner-layer pads be than outer-layer pads?
No fixed number here, because it depends on layer count, board thickness, drill size and construction. The usable method is to work backwards from the published inner-layer hole-to-copper figure of drill size + 0.020" to your own minimum acceptable ring, then confirm it in engineering review.
Q: Does more layers mean more misregistration?
More layers increase both dimensional variation and the number of accumulation opportunities in lay-up, so high-layer-count boards generally need more conservative inner-layer clearance. SKPCB runs to 40 layers in standard volume production, with HDI and high-layer-count structures up to 64 layers — a range that requires engineering review.
Q: Doesn't X-ray targeting eliminate layer shift?
No. X-ray reads where the inner layers actually are and establishes the drill datum, so the offset gets measured and compensated. Displacement that already happened under press does not reverse because you measured it.
Q: What is the single thing to settle first at design time?
The datum system and the inner-layer targets. Those two decide whether the fabricator can know accurately where your inner layers are. Leave them vague and every clearance calculation downstream rests on a guess.