Once a Rogers laminate is selected, the next step is the stackup and impedance calculation. The datasheet shows two dielectric constants: Process Dk and Design Dk. For the same material they often differ, and Design Dk is usually the higher one. Which value goes into the field solver sets the trace width, and it decides whether the finished board's TDR results land on target or shift as a whole.
That kind of error is systematic: every board in the lot and every line of the same type moves in the same direction. The cause is usually not etching or lamination at the fabricator. It is a mismatch between the Dk used in design and the Dk the fabricator uses to check the build.
Where the two Dk values come from
The difference lies in the test method, not in the material.
- Process Dk is measured with the clamped stripline method of IPC-TM-650 2.5.5.5, on raw laminate at a specified frequency. Its job is quality control of laminate production: is a lot consistent and within specification?
- Design Dk is obtained by Rogers with a microstrip differential phase length method on fabricated circuit samples, over a frequency range. It includes the effect of real conductors, including copper surface roughness, so it is closer to the effective dielectric constant a circuit actually sees.
Rogers' own guidance is to use Design Dk for circuit design. Process Dk is not wrong data. It answers a different question.
Why Design Dk is usually higher
Copper foil is not smooth. Electrodeposited and reverse-treated foils both have measurable roughness. At high frequency, current crowds into the skin depth at the conductor surface, and a rough surface lengthens the current path and slows the phase. That appears as a higher effective Dk. The clamped stripline test does not capture this, so Process Dk reads lower.
Two design consequences follow:
- Foil type changes effective Dk. The same laminate with a different foil roughness can have a different Design Dk. The datasheet Design Dk refers to a particular foil, so the stackup drawing should name the foil type. Otherwise the fabricator may stock its default foil.
- Thinner dielectrics feel the foil more. In a thin dielectric, the conductor surface makes up a larger share of the field. With thin cores and fine lines, the gap between Process Dk and Design Dk has a larger effect on impedance.
The effect of foil roughness on insertion loss is covered in copper foil roughness and insertion loss. This post covers only its effect on Dk and impedance.
Frequency: which point on the datasheet?
Dk varies with frequency. Rogers usually gives Design Dk as values or a curve across a frequency range. Impedance calculations should use a value near the circuit's operating frequency, not the single number on the first page of the datasheet.
For circuits spanning a wide band, note on the stackup drawing which frequency the calculation used and whether several frequencies were checked. Then the fabricator's back-calculation uses the same point.
After lamination, dielectric thickness is not datasheet thickness
Impedance is sensitive to dielectric thickness, often more than to Dk. Finished dielectric thickness depends on:
- Core thickness: Rogers cores carry a thickness tolerance. Calculate with the nominal value, but remember it is not zero-tolerance.
- Bondply or prepreg: in multilayer Rogers builds or hybrid builds with FR-4, the bonding layer flows during pressing, and its final thickness depends on the residual copper of the neighbouring layers. Its Dk also differs from the core.
- Copper thickness: plated finished copper on outer layers changes the trace cross-section and the fringing field.
So in the calculation, use Design Dk for the core, the bonding material's own Dk for the bond layer, and pressed thickness for the dielectric. The fabricator usually has to confirm these three from its own lamination data. Process constraints for hybrid builds are covered in hybrid PCB mixed-material stackup and lamination.
What to put on the stackup drawing
The stackup drawing is the only document that aligns designer and fabricator. For impedance, include at least:
| Item | How to state it |
|---|---|
| Material | Full grade and thickness, e.g. an RO4350B core of a given thickness; whether equivalents are allowed |
| Copper foil | Copper weight and foil type, if the calculation assumes a specific roughness |
| Dk used | Value, source (Design Dk / Process Dk), frequency, datasheet revision |
| Bond layer | Material grade, Dk used and pressed thickness |
| Impedance lines | Layer, reference planes, target impedance, tolerance, single-ended or differential |
| Verification | Coupon location and TDR test requirement |
The item most often left out is the source of the Dk. A bare number tells the fabricator nothing about whether it is Process Dk or Design Dk. The fabricator may back-calculate with the other value and adjust widths on that basis, and each side ends up believing the other made the error.
If the designer wants the fabricator to adjust widths from its own lamination data to hit impedance, the drawing should state what may be adjusted and by how much, for example trace width only, no change to dielectric thickness.
How to verify: TDR and the trace-back order
Finished impedance is verified by TDR (time domain reflectometry) on impedance coupons. A coupon shares layer, reference and width with the board's lines, so it measures the actual impedance of the physical structure. Coupon design and report reading are covered in impedance test coupon verification.
When measurements are off target as a whole, trace back in this order:
- Basis: did the design calculation and the fabricator's back-calculation use Dk from the same source at the same frequency? This is the most common cause of a systematic shift.
- Dielectric thickness: measure pressed thickness by microsection and compare with the calculation.
- Width and copper: measure finished top and bottom width and copper thickness.
- Test conditions: check TDR rise time and the measurement window against what was agreed.
Only after these are ruled out does a laminate lot problem become a likely explanation.
SKPCB high-frequency and impedance capability
- RF laminates: Rogers 4350B, 4003C and 3003, Arlon 85N, Taconic RF-35 (
MAT-RF). - Impedance tolerance: ±10% standard, ±5% advanced (
PCB-IMPEDANCE). - 100% electrical test on all orders (
Q-ETEST).
Choosing a tolerance class is covered in impedance control tolerance classes. Drilling, plating and lamination differences across Rogers families are in Rogers RO4000 vs RO3000 fabrication differences. For a stackup review, submit the drawing and impedance requirements via the quote page, or see high-frequency PCB and materials.
Summary
- Use Design Dk for circuit design. Process Dk is for laminate quality control.
- Foil type, frequency, bond layer and pressed thickness all change the result, so put them on the stackup drawing.
- State the Dk source and frequency so the fabricator back-calculates on the same basis.
- When results shift, check the basis first, then thickness, width and test conditions.
FAQ
Q: Should Rogers impedance calculations use Process Dk or Design Dk?
A: Design Dk. It is measured on circuit samples, includes the effect of copper roughness and is closer to what the circuit sees. Process Dk is for laminate production control.
Q: Why is Design Dk higher than Process Dk?
A: The test methods differ. The Design Dk test includes real conductors, and rough foil lengthens the high-frequency current path and slows the phase, which shows up as higher effective Dk. The clamped stripline method does not capture that.
Q: What if the datasheet gives only one Dk?
A: Find out the test method and frequency behind it. If that cannot be confirmed, state the value and its source on the stackup drawing and ask the fabricator to confirm by back-calculation from its lamination data.
Q: Does a different copper foil change Dk?
A: Effective Dk changes, especially in thin dielectrics. The datasheet Design Dk refers to a specific foil, so name the foil type on the drawing.
Q: May the fabricator adjust trace width to hit impedance?
A: It can be agreed. State on the drawing what may be adjusted and within what range, for example trace width only, with no change to dielectric thickness.
Q: TDR results are high or low across the board. What should be checked first?
A: Whether design and fabricator used Dk from the same source and frequency. Then pressed dielectric thickness, finished width and copper, and TDR test conditions.