#### 1. Why impedance is proven on a coupon, not on the production board
Characteristic impedance is not something you can casually probe on a finished board. Production traces are short, terminated into component pads and vias, and a TDR probe placed there returns a waveform contaminated by pad capacitance, via stubs, and corner discontinuities. The number you read is not the impedance of the trace itself. Getting a clean reading requires a long, structurally uniform, open-ended trace. That is exactly what a test coupon provides.
The coupon is a small auxiliary area placed on the same manufacturing panel as the production boards. It shares the same laminate lot, the same lamination cycle, the same etch, and the same plating. That shared process history is the entire source of its value. A coupon fabricated on a separate panel, or built on a different stackup, is no longer representative and its numbers prove nothing about your boards.
This framing answers two questions buyers ask constantly. "Can we skip the coupon and save panel area?" You can, but then the lot ships without impedance evidence, and if a signal integrity problem shows up later there is no way to separate a fabrication issue from a design issue. "Why does every panel need one?" Because laminated dielectric thickness and etched line width drift between panels, and sometimes across regions of a single panel. One panel's reading cannot vouch for another's.
#### 2. What actually goes on a coupon
A usable coupon is not an arbitrary length of trace. Every controlled-impedance structure on the drawing needs its own sample group. Four structures cover most designs:
Single-ended microstrip. Trace on an outer layer, reference plane on the adjacent inner layer, air or soldermask above. This structure is sensitive to soldermask, so the microstrip samples on the coupon must carry the same surface condition as the production traces.
Single-ended stripline. Trace on an inner layer with reference planes above and below. Sensitive to dielectric symmetry, which makes it the structure where lamination shift shows up first.
Differential microstrip and differential stripline. Coupled pairs where the controlled parameter is differential impedance. Beyond line width, the gap matters just as much: etch the spacing off target and differential impedance moves with it.
However many distinct impedance requirements appear on the drawing, that many sample groups belong on the coupon. In practice engineering renders each structure as a straight run long enough to give the instrument a stable measurement window, terminated in probe-friendly pads. How many groups per structure and where they sit on the panel are details settled during engineering review, and they vary by fabricator and by drawing.
#### 3. Reading a TDR report field by field
When a report arrives, resist jumping to the PASS/FAIL column. A report worth accepting answers five questions.
Which trace was measured? Each row should map to a specific impedance requirement ID or net name from the drawing. If the report says "L1 single-ended 50Ω" while your drawing has three different 50Ω widths on that layer, the row cannot be reconciled and you should ask for clearer identification.
What are the target and tolerance? The target comes from your drawing. If the drawing leaves tolerance blank, the fabricator's standard capability applies. Sanqiang Circuit's standard impedance control tolerance is ±10%, with ±5% available as a tighter grade subject to engineering review (claim_id PCB-IMPEDANCE). Note that tolerance is a percentage of target: a 50Ω target at ±10% accepts 45–55Ω, while a 100Ω differential target at ±10% accepts 90–110Ω. Absolute acceptance windows differ across targets on the same drawing.
How are the measured values distributed? A good report lists every sample point, not just an average. Distribution tells you more than the mean. Five points clustered at 52–53Ω indicate a stable process with a predictable systematic offset, correctable on the next build. Five points scattered from 46 to 54Ω, even averaging exactly 50Ω, indicate a consistency problem that will likely push points outside the limit on the next lot.
Under what conditions? TDR results depend on probe rise time and where in the waveform values are taken. The report should identify the instrument, ambient conditions, and the extraction method. When you re-measure and disagree with the fabricator, this is the only basis for aligning methodology.
Where were samples taken? Readings vary across panel position. Without location data you cannot tell a global shift from a local one.
#### 4. The four process variables behind every impedance shift
When a report shows an offset, the root cause almost always sits in one of these four. Knowing which direction each one pushes makes supplier conversations much faster.
Dielectric thickness. More distance from trace to reference plane raises impedance. That distance comes from prepreg type, ply count, and the pressed thickness after lamination. Lamination drift shows up as a shift affecting the whole lot uniformly.
Line width. Wider trace, lower impedance. This is where design meets manufacturing: the drawing carries the design width, etching delivers the actual width, and an etch compensation factor bridges the two. Standard line width tolerance is ±20% (claim_id PCB-TRACE-TOL), which is wide enough to matter for impedance, and is precisely why fine-line boards are harder to control.
Copper weight. Heavier copper produces a more pronounced sidewall effect and a steeper trapezoidal cross section after etch, shifting effective impedance. Heavy copper combined with tight impedance control deserves specific attention at engineering review.
Dielectric constant (Dk). Higher Dk lowers impedance. Dk within a single laminate family also varies with frequency, so high-speed work needs the Dk value for the relevant band rather than the first line of the datasheet. For how laminate choice feeds into this, see high-frequency PCB material selection.
#### 5. When a reading is out of spec: closing the loop
Handling an out-of-limit value breaks into three steps.
Step one: confirm it is a real deviation. Reconcile target and tolerance against the current drawing revision. A meaningful share of reported deviations trace back to the fabricator working from a superseded target, or to a blank tolerance field filled in with a different default. Then verify the structure matched: measuring a differential pair as single-ended, or probing the wrong layer, produces numbers that look out of spec but are not. Comparing the identification columns against the drawing clears most cases.
Step two: characterise the offset. A uniform high or low shift points to dielectric thickness or Dk, correctable by adjusting the stackup on the next build. Scatter without pattern points to etch or plating consistency, which requires the fabricator to review process control. This distinction determines whether the fix is a stackup change or a process change, and it also settles the rework question: impedance deviation cannot be repaired on finished boards, only corrected before the next build starts.
Step three: run a formal nonconformance process. Ask for root cause analysis, an impact assessment stated against your actual signalling rate, corrective action, and a verification plan for the next lot. In parallel you make the deviation call on your side: is this lot usable? That decision rests on your own signal margin, not on the fabricator's assurance.
Worth saying plainly: most impedance disputes are avoidable before release to manufacturing. Ask for a stackup proposal up front, align target impedance, recommended widths, prepreg configuration, and predicted values in writing, and confirm it. That is far more effective than arguing over a report afterwards. For the surrounding process controls see quality control, and for tolerance definitions see manufacturing tolerances.
#### 6. Five things to specify on the drawing
- Scope of each impedance requirement. Name the layer and the nets or widths it applies to, so report rows can be reconciled.
- Target and tolerance. Do not leave tolerance blank. Standard ±10% applies by default; if your margin demands tighter, mark it and confirm feasibility at review.
- Coupon requirements. Whether coupons are required, which structures, and whether physical coupons ship with the order.
- Report content. Per-point values or summary only, and whether instrument and condition data are required.
- Deviation handling agreement. Whether out-of-spec means automatic rejection, or an analysis first with the deviation call left to you.
Settling these at order placement costs far less than negotiating after delivery. For product-level capability see impedance control PCB; for the design-side stackup and width calculations, see impedance control PCB design.
FAQ
Q1: Do coupons have to ship with my boards?
Not necessarily; it depends on the order agreement. Their core function is to let the fabricator issue a representative report, and the report usually suffices. If you intend to re-measure yourself, specify physical coupon delivery at order placement, because coupons are part of the panel and are normally separated during routing.
Q2: Should I ask for ±10% or ±5%?
Start from your signal margin. ±10% is the standard capability (PCB-IMPEDANCE) and covers most conventional-rate designs. If your link budget is genuinely sensitive to impedance variation, ±5% can be requested as a tighter grade, with feasibility confirmed at engineering review against stackup and width. Tighter is not automatically better: it means more stackup iteration and higher scrap exposure.
Q3: Why does my own TDR reading differ from the fabricator's report?
Three usual causes: a different measurement location (production trace versus coupon), different probe rise time and extraction window, and whether pad and via effects are included. Aligning results requires both parties to measure the same coupon with the same extraction method. This is why condition data on the report is not optional.
Q4: Can out-of-spec boards be reworked to bring impedance in?
No. Impedance is set by dielectric thickness, line width, copper weight, and Dk, all locked in once lamination and etching are complete. The workable path is assessing whether the lot can ship under deviation, while adjusting stackup or etch compensation before the next build.
Q5: Is single-ended 50Ω the same as differential 100Ω?
No. Differential impedance is not twice the single-ended value; the relationship depends on coupling between the two traces. Tighter spacing means stronger coupling and comparatively lower differential impedance. Specify both separately on the drawing and sample both separately on the coupon.