A castellated hole is a plated hole intentionally cut by the board outline, leaving a half or partial barrel at the edge so a module PCB can be soldered directly onto a motherboard. This is a different interface class from a gold-finger edge connector: gold fingers serve a repeatedly mated socket and are judged on finish and wear, while castellations serve a one-time solder joint and are judged on whether the plated barrel stays continuous, solderable, and inspectable after it has been cut. Design review should start from that functional definition rather than moving an ordinary via to the board edge.
Documentation is where castellated designs most often break down. Manufacturing needs to know explicitly which holes are castellated, how the cut line relates to each hole centre, how the outline is defined, whether solder mask may cover the castellated region, how castellated copper relates to adjacent copper and legend, and whether the castellations are part of electrical test. Gerber layers alone rarely carry that intent. Supply a dimensioned mechanical and profile drawing alongside the layer data, and mark values that still need engineering confirmation. Do not leave the fabricator to reverse-engineer the cut position.
Surface finish and mask strategy belong to the same discussion as the solder joint. Castellation solderability depends on barrel copper continuity and on whether the selected finish reaches the exposed cut section, which in turn interacts with the finish type, the mask opening approach, and edge cleanliness. Record the specified finish, the mask strategy in the castellated area, any cosmetic requirement covering burrs or copper debris, and the acceptance reference used at inspection. This draft sets no finish type or thickness; anything the specification does not state should become an open item rather than a fabricator assumption.
Castellations also interact with panelization and profiling. Because they sit on the outline, they are affected by the profiling path, the panel connection method, and the separation step, and those choices can change edge loading and the visual quality of the cut barrel. Review the mechanical drawing, profiling intent, panel requirement, module placement orientation, and motherboard pad design together, and state who owns the motherboard-side land pattern and stencil. Packaging the source files, Gerber, drill data, mechanical and profile drawings, stackup, finish requirement, test requirement, and open-item list together removes most clarification loops.
Related reading: align edge and profiling callouts on the PCB tolerance and finished-dimension page, discuss solderability-related finish choices on the PCB surface finish page, and use the Gerber file preparation checklist to assemble the handoff. Submit a reviewed package through the online quote page. Verify every route and locale before publishing.
FAQ
Are castellated holes the same as edge plating?
No. Edge plating generally means a continuous metal layer along the board edge, often for shielding or grounding. A castellated hole is an individual plated hole cut by the outline, used to solder a module to a motherboard. Their drawing callouts, profiling requirements, and acceptance concerns differ and should be stated separately.
Can castellation diameters and cut positions reuse standard via parameters?
Not advisable. A castellation must satisfy electrical connection, solder access, and post-profiling section quality at once. Diameters, cut position, and tolerances come from the project drawing and engineering confirmation; no defaults are given here.
What is most often missing from the data package?
Typically a missing mechanical or profile drawing, no indication of which holes are castellated, no stated mask and finish strategy for that region, and no cosmetic acceptance reference. Close those gaps during review.
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Mechanical drawing review of castellated half holes along a module PCB outline