The short version: where a microvia sits in z does not decide whether routing is convenient, it decides which process step carries the cost. Stacking puts the cost at the via bottom — the next via lands on the fill surface of the one below, and how flat and solid that surface is decides whether you can keep going. Staggering puts the cost in the plane — moving a via sideways requires somewhere to move it, and capture pads and routing channels have to give up the space. Anylayer puts the cost in lamination cycles — every additional interconnectable layer pair is another press and another registration round. None of the three is "more advanced." They differ only in where the cost is cheaper for your board.
1. The difference is in the process order, not the drawing
In the routing tool these three structures look like nothing more than different via positions. In the factory they are three different process paths.
HDI microvias are built layer by layer: start from a core, press a dielectric and copper layer outward, laser the vias, plate, image; then press the next layer, laser again, plate again. The decisive point is this — the via in layer n+1 is drilled only after layer n is complete. So whatever surface condition layer n leaves behind becomes the starting point for the laser and the plating of layer n+1.
- Stacked: the layer n+1 via sits directly above the layer n via. The laser now fires at the "lid" of the previous via, and the plating has to grow copper on that lid.
- Staggered: the layer n+1 via moves sideways and lands on an intact copper surface. Laser and plating face a conventional starting point.
- Anylayer: no assumption about which layer pairs may interconnect; any adjacent pair can carry a microvia, and the structure is normally built up sequentially.
One sentence for all three: stacked saves plane and spends via bottom; staggered saves via bottom and spends plane; anylayer wants both and spends lamination cycles.
This also clears up a common misreading. People sometimes treat anylayer as "stacking taken to the extreme." Anylayer actually describes interconnect freedom, while stacked and staggered are two ways of realising that freedom. An anylayer structure typically contains both, and both have to work on the same board. On the cost of build-up count itself, the three real costs of sequential lamination have their own article and are not repeated here.
2. Stacked: the via bottom is another via's lid
The entire difficulty of stacking fits in one sentence: the next via has to land on the fill surface of the one below.
After plating, the lower via is a depression. For the next via to be built reliably on top of it, that depression first has to become a surface that is flat enough, solid enough and supportive enough. Stacking therefore pulls two things onto the critical path:
- Whether the fill is dense. Any unfilled region inside the via becomes a cavity during the subsequent presses and thermal excursions. That cavity sits directly under the next via — precisely where the structure sees the most concentrated mechanical and thermal loading.
- Whether the surface is planar. Filling is normally followed by planarisation. If a visible depression remains, the laser fires into the bottom of a bowl, which affects energy distribution and via shape; plating then grows copper from an irregular starting point.
Neither is judged by visual inspection. They are judged in cross section. Fill and dimple acceptance criteria for resin-filled vias are covered separately, and stacked structures depend on those criteria more heavily than ordinary plugged vias do — because the step after an ordinary plugged via is solder mask, while the step after a stacked via is another via.
So on the manufacturing side, the real constraint on stacking is rarely "can it be stacked." It is how many levels in the accumulated via-bottom deviation can still support the next laser and plating pass. Planarity deviation propagates upward from every level; it does not cancel itself out.
3. Staggered: the cost moves from the via bottom to the plane
Staggering sidesteps that problem entirely: the next via does not land on the one below but moves to an intact copper surface beside it. The laser faces a conventional starting point, the plating faces conventional geometry, and the via bottom leaves the critical path.
The cost appears at the same moment, just somewhere else — moving requires somewhere to move to.
- Every stagger level consumes plane area. A microvia needs a capture pad, the capture pad needs clearance, and that clearance competes with surrounding traces, neighbouring vias and component pads for the same space.
- Staggering effectively splits a z-axis connection into "via + a short trace + via." That trace needs a channel.
- The more stagger levels, the more area consumed — and consumed exactly in the layers where area is scarcest, usually the BGA fanout region.
One point deserves emphasis: capture pad size is not only an electrical requirement, it is also registration allowance. Positional deviation of a laser via relative to inner-layer features has to be absorbed by the capture pad, and that allowance cannot be squeezed away to save area. In other words, the via-bottom risk that staggering saves cannot all be converted into smaller capture pads — otherwise the risk has only moved from one process step to another.
The decision rule compresses to this: if the board still has plane margin in the fanout region, staggering is usually the cheaper choice; if the plane is already full, squeezing further means trading registration allowance for area, and that is the point where stacking earns its cost.
4. Anylayer: every layer is a press, and the accumulation grows with it
The appeal of anylayer is direct: any adjacent layers can interconnect, so routing is barely constrained by layer pairing. The manufacturing fact is equally direct: that freedom is bought with repeated lamination.
Every "press — laser — plate — image" round adds three things:
| Accumulating item | Why it accumulates | Where it lands |
|---|---|---|
| Interlayer registration deviation | Every press has its own material movement and dimensional change | Position of outer features relative to the innermost layer |
| Thermal history | Every round goes through a full lamination temperature cycle | Materials and already-formed via structures |
| Surface condition deviation | Every round's fill and planarisation leaves its own residual | Starting point for the next laser and plating pass |
The first row is the one most often underestimated. Misregistration does not come from a single source; it is material movement, scaling compensation and image positioning combined, and more rounds mean more combinations of those sources. They do not add up as a simple sum, but they certainly do not cancel.
The second row carries a different class of risk. Repeated lamination heat tests both the dielectric and the already-formed via structures, and preventing delamination and voids is a core concern of the lamination step in its own right. In an anylayer structure the innermost layers see the most rounds — what is built first endures the most cycles.
There is one more practical constraint that often gets skipped: the available dielectrics and prepregs are a discrete list, not a continuum. Stackup planning is really an exercise in hitting a thickness from a finite material list. An anylayer structure places requirements on every dielectric layer, and those requirements have to be buildable from stock constructions. This is frequently discovered only during engineering review.
5. Which limits come from the laser, which from fill and planarisation, which from lamination
Sorting the constraints by process step tells you who to ask during review:
- From laser drilling: via shape and wall condition, cleanliness of the via bottom, positional deviation relative to inner-layer features. This class weighs most on stacked structures, because a stacked laser pass starts on the fill surface of the previous via.
- From fill and planarisation: fill density, surface planarity, residual depression. This class is on the critical path almost exclusively for stacked structures; staggered vias may also require filling, but fill quality does not decide whether the next via can be built.
- From plating: copper continuity and distribution along the wall, difference between mouth and bottom. This class exists for all three, but whether microvia aspect ratio is set by the laser or by the plating is a separate question and through-hole conclusions do not transfer. Copper thickness itself has a design-input layer to settle first: base foil, finished copper and via wall copper are not one number.
- From lamination: interlayer registration, resin flow and fill, accumulated thermal history. This class weighs most on anylayer, because it has the most rounds.
The use of this table is practical: when a factory says "this structure carries risk," you can ask which class the risk falls into. The four classes are handled very differently — laser and plating classes can often be addressed inside the process window, fill and planarity classes depend on whether the structure left margin, and lamination accumulation classes usually require a structural change.
6. What cross section shows and electrical test does not
This section is worth isolating, because it is where stacked structures most often go wrong.
Electrical continuity testing answers "is it connected now." A stacked via with a defective bottom but a partial connection still passes. The defect is that the connection's cross section is smaller than the design intent, and a small cross section fails first under thermal cycling and mechanical stress.
Cross section answers "what did the structure actually become." The connection geometry at the via bottom, whether the fill is dense, whether the stacked vias really align, whether the copper is continuous — these are only visible in section. That is why engineering confirmation of a stacked structure almost inevitably involves microsection rather than release by electrical test. On where microvias fail, we have written separately that failures happen at the via bottom, not in continuity test.
The gap between the two is exactly where the risk lives: the typical failure mode of a stacked structure falls precisely in the band that electrical test cannot see and only cross section can. So if a project's verification plan consists of electrical test alone, the risk introduced by stacking is invisible at delivery and surfaces later, during temperature cycling or extended service.
The practical implication is concrete: the more a structure relies on stacking, the more microsection evidence engineering confirmation needs — and microsection is destructive, requiring sacrificial samples. That belongs in the quoting and scheduling conversation, not in a pre-shipment discussion. For the broader inspection and release logic, see the quality page.
7. Mixing stacked and staggered on one board
Real HDI boards are rarely purely stacked or purely staggered. The common approach is: stack where the plane is tightest, stagger where margin remains.
That mix is reasonable, but two things have to be settled in advance:
- The factory plans its process around the most demanding location on the board. As soon as one site requires stacking, fill and planarisation enter the critical path and the whole panel follows that route. So "only a small region uses stacking" does not translate into "only a small region's cost."
- Mixing makes the stackup table more complex, and the stackup table is what gets signed off. Which layer pairs may stack, to how many levels, which regions must stagger — if that only exists in the routing files and not in the stackup table, the factory has to infer it, and inference creates ambiguity.
So the prerequisite for mixing is this: the stackup table has to be readable on its own, without opening the routing files to guess.
8. What the stackup table and drawing must state
This is the most actionable section. To let a factory sign off an HDI structure, the following have to be stated explicitly; every missing item becomes a clarification round:
- Role and order of each layer: which layer is the core, which are sequentially built up. This is the prerequisite for reading the structure at all.
- Which layer pairs carry microvias: listed pair by pair. "Three-level HDI" is a summary, and a summary is not enough to reconstruct the structure.
- Stacked/staggered declaration: which microvias may stack and to how many levels; which must stagger. If there is no restriction, state "no restriction" rather than leaving it blank.
- Extent of through vias: whether a through hole spans the full board, and how it coexists with the microvia structure.
- Ownership of fill requirements: which vias must be filled, and whether the fill is structural or surface-related. Fill beneath a stacked via is the former and must not be written together with mask plugging.
- Capture pad and registration allowance agreement: pad size, and whether it already includes registration allowance. When this is unstated, both sides assume their own version.
- Target dielectric thicknesses and acceptable range: and whether those thicknesses have been checked against available constructions.
- Which requirements are hard and which are negotiable: often omitted, but it decides whether the factory asks repeatedly or simply proceeds. Give priority and review closes in one round.
Finished board thickness also needs to be stated — it is an outcome of the stackup rather than a free variable, and it carries tolerance. For the overall capability envelope start with the manufacturing capabilities page; for structure selection start with the HDI product page and the multilayer page.
9. When to change the structure instead of pushing the process
A closing decision rule. When an HDI structure is flagged as high risk during review, there are two paths: let the factory absorb it inside the process window, or change the structure. Change the structure in these cases:
- When the cost comes from accumulated lamination rounds. Registration and thermal accumulation are not process-window problems; they are functions of round count. Reducing the number of interconnected layer pairs is more realistic than asking the factory to make every round tighter.
- When stack level was driven by routing convenience rather than functional need. Ask first: is this stack level required, or is rerouting simply more work? If the latter, rerouting usually costs less than carrying via-bottom risk into volume production.
- When the plane is full because capture pads were squeezed below the registration allowance. Staggering further then transfers risk to registration rather than solving anything.
- When the verification plan cannot support the structure's complexity. If the project has no budget or schedule for microsection confirmation, reliability should not be staked on a structure that only microsection can verify.
Conversely, if the cost sits mainly in the laser and plating process windows while the structure itself has clear layer pairing and declared margin, it is usually worth letting the factory handle it on the process side rather than re-laying the structure.
The whole thing reduces to one question: is the cost of this board chosen, or has it simply landed somewhere by default? All three arrangements are manufacturable. The difference is only whether the cost sits where you knew about it and prepared for it, or where you find it in a cross section.
FAQ
Q1: Is stacking "more advanced" than staggering?
Neither is more advanced. Stacking saves plane area at the cost of putting fill and planarisation on the critical path; staggering removes via-bottom risk at the cost of plane area and capture pad budget. The choice depends on whether your board is short of area or short of margin.
Q2: Is anylayer just stacking on every layer?
No. Anylayer describes interconnect freedom — any adjacent layer pair may carry a microvia — while stacked and staggered are two ways of realising that freedom. An anylayer structure typically contains both, and both must work.
Q3: Why do factories pay such close attention to fill quality on stacked vias?
Because the next via is built on the fill surface of the one below. Incomplete fill leaves a cavity directly under the next via, and a non-planar surface makes the laser fire into a depression and the plating start from an irregular base. The step after an ordinary plugged via is solder mask; the step after a stacked via is another via.
Q4: Does the extra trace in a staggered connection hurt performance?
Staggering splits a z-axis connection into "via + short trace + via," so there is an additional path segment. Whether that matters depends on the electrical requirements, which is a design-side judgement. The manufacturing-side concern is whether that trace has a channel and whether capture pad clearances still fit.
Q5: If only a small region uses stacked vias, is the cost increase also small?
No. The factory plans around the most demanding location on the board. As soon as one site requires stacking, fill and planarisation enter the critical path for the entire panel. Local use of stacking produces a panel-wide process change.
Q6: If electrical continuity passes, is the stacked structure sound?
That conclusion does not follow. Continuity answers "is it connected now," while the typical stacked-via risk is a connection cross section smaller than design intent — which passes continuity but fails first under thermal cycling and mechanical stress. Cross-section evidence is needed to confirm structure.
Q7: Is "three-level HDI" enough on the stackup table?
No. Build-up level is a summary and does not let the factory reconstruct the structure. List layer pair by layer pair which carry microvias, which may stack and to how many levels, which must stagger, plus through-via extent and ownership of fill requirements.
Q8: Can dielectric thickness be specified freely?
No. Available cores and prepregs form a discrete list, so stackup planning is an exercise in hitting a thickness from a finite set. Before specifying a dielectric thickness, confirm it can be built from available constructions, otherwise it comes back during engineering review.