The conclusion first: the failure location of a microvia can be named in advance. It is at the bottom of the via, at the interface where plated copper meets the target pad. Not mid-wall, not at the via mouth, and not at the diameter you measured during inspection.
This gets overlooked because the via-bottom interface is an invisible pass at outgoing inspection. Electrical test reports continuity at this moment. Flying probe, ICT and net testing all come back clean. But continuity is a binary result, and it does not distinguish between a via bottom that is fully bonded and one where only a narrow ring of copper is barely attached. Those two boards produce identical test reports on the day they ship. The difference appears later, in the field, after enough temperature excursions.
The resulting field failure has a recognisable signature: the board works at commissioning, then begins failing intermittently after months of service, often correlating with temperature. The root cause traces to a group of microvias going open, each of which was inspected and passed.
1. Why Failures Concentrate at the Via Bottom
A microvia is a shallow, blind, bottom-terminated hole. Mechanically it is not the same object as a through hole.
A through hole is open at both ends, and its wall copper forms a continuous barrel. As the laminate expands in Z, it pushes against the whole barrel and the stress distributes along the hole length. A microvia has one opening only. Its bottom is a flat target pad, and the plated copper must land on that plane. Consequently nearly all of the Z-axis expansion the via experiences is carried by that one small bonded area at the bottom.
The laminate's Z-axis coefficient of thermal expansion is far higher than copper's. On heating, the dielectric above the via bottom drives the plated column upward; on cooling it pulls it back. This is not a single large force but a small one repeated every cycle. Any initial defect in the bond area — even a narrow unbonded ring — becomes a crack initiation site that propagates along the interface until the conductive path is severed.
That is why microvia life problems almost always present as opens after thermal cycling rather than as opens at manufacture. Whether a via is open is a process capability question, visible the same day. Whether its bottom is well bonded is a reliability question, and only accelerated testing surfaces it.
2. The Via Bottom Is the Product of Three Processes
No single operation owns the condition of the via bottom. It is the end result of a short chain, and drift anywhere on that chain lands on the same interface.
Link one: what shape the laser leaves, and what residue.
The laser opens the dielectric and must terminate at the bottom — it has to clear the dielectric and stop on the target pad. How it stops determines two things: the sidewall profile, and whether modified resin remains at the bottom.
Via profile is not a cosmetic matter. Walls that are too steep impede effective solution exchange at the bottom. A pronounced taper, wide at the mouth and narrow at the base, skews current distribution so plating accumulates toward the mouth and thins at the bottom. As for residue, the laser's thermal action leaves behind resin with damaged structure plus carbonised products. That layer is not conductive and is not a reliable bonding substrate. If copper plates directly onto it, the interface is defective from day one.
Link two: desmear must land inside a window bounded on both sides.
Desmear exists to remove that residue and to present the target pad with a surface that can be bonded to. Its difficulty is that both directions are bounded.
Clean too little and the residue stays in the interface, separating the bond with an intermediate layer. Clean too much and the target pad itself is attacked while the dielectric is over-etched, leaving the via bottom with rough, uncontrolled topography that introduces new stress concentrators. Desmear has no "a bit more is safer" option. It must land inside a window, and the window's position shifts with material system, via geometry and equipment condition.
This is why parameter stability matters more here than the parameter value. A process that sits consistently mid-window is materially more reliable than one probing the window edge each batch, even when both yield passing inspection results.
Link three: plating must grow dense, grain-continuous copper at the bottom.
Inside a microvia, plating faces a geometry hostile to mass transport. The bottom is furthest from the bulk solution, exchange is slowest, and additive distribution differs from the mouth. Two problems follow: insufficient coverage, where plating thins or becomes discontinuous at the bottom; and abnormal grain structure, where copper of nominally adequate thickness has coarse grains or an internal boundary and cracks earlier under cyclic stress.
Adequate thickness is not an adequate interface. A cross-section can simultaneously show conforming bottom plating thickness and a discontinuous line between that plating and the pad. The former is a dimension; the latter is a bond. A report carrying only the former has not answered the reliability question.
3. Stacked or Staggered: Stress Aligned, or Offset
Once HDI goes beyond a single level, via arrangement directly changes stress concentration.
Stacked vias place each level's microvia directly above the one below. The benefit is concrete: routing area saved, signal path shortened, and for high-density designs it is close to mandatory. The cost is that every level's via-bottom interface lines up along Z, so thermal expansion transmits along one axis and the levels' stresses are not independent. The lowest via bottom carries not just the dielectric immediately above it but the accumulated effect of the whole column. Whichever level has a defective bottom becomes the first link to break.
Staggered vias offset each level laterally so adjacent bottoms do not share a vertical line. The stress path is interrupted and each bottom faces only its own overlying dielectric, without superposition. The cost is equally concrete: more routing area, longer paths, and sometimes an extra routing layer.
There is no universally correct answer, only a trade: stacked buys density and pays in stress concentration; staggered buys stress distribution and pays in area. The decision to be made is whether this board's pressure is density or thermal cycling severity. It must be made before routing, because reversing it means re-laying out the region.
The engineering discussion of that trade — how level count, registration and dielectric thickness jointly constrain structure selection — is developed separately elsewhere. This article is concerned only with its effect on via-bottom stress.
4. What Thermal Cycling Proves, and What It Does Not
Since failure requires cycling to surface, the verification method follows naturally. But its evidentiary limits need stating, or a passing report gets read as a stronger guarantee than it is.
What it does prove: under the specific set of conditions applied, the samples' via-bottom interfaces did not fail within the specified cycle count. Combined with resistance trend before and after, it is a sensitive indicator of interface degradation, because crack propagation shows first as slowly rising resistance and only later as an open. Resistance drift gives the signal earlier than final continuity does, and that is the most valuable part of this class of test.
What it does not prove, in three parts:
First, it does not extrapolate to different temperature ranges or ramp rates. Accelerated conditions and field conditions are two different load sets. Passing the former does not automatically mean passing the latter. Extrapolation requires a reasoned correspondence, not the sentence "thermal cycling passed."
Second, it does not represent the lot. The test uses samples, usually drawn from particular locations. It demonstrates that this process on this batch is capable of producing conforming via bottoms, not that every microvia in the lot conforms. What actually covers the lot is process control stability and sampling representativeness, not the pass line on the report.
Third, it does not replace sectioning the interface. Passing electrical performance after cycling and sound interface morphology are two distinct pieces of evidence. An interface may have partially propagated without severing, and electrical test still passes. Cycling and post-cycling cross-sections belong together: the first indicates life, the second gives mechanism.
5. So What Should You Ask When Qualifying an HDI Supplier
Translating the causal chain above into executable questions gives roughly this set:
- On direct via-bottom evidence: are post-cycling bottom cross-sections provided, not just pre-cycling dimensional sections? Can the plating-to-pad interface morphology be seen, not only a thickness reading?
- On the desmear window: how are this operation's parameters monitored? Is it covered by final inspection, or is there process-level stability data?
- On structure selection: when a design specifies stacked vias and the service environment cycles hard, will the factory proactively propose staggering? Or build to print and leave the reliability risk with the designer?
- On failure history: can they describe microvia failure modes they have encountered and the corrective actions taken? A supplier that never mentions failures has usually just never run accelerated testing.
None of these ask about level count or equipment models, because those answers cannot differentiate suppliers. What differentiates them is whether they treat the via-bottom interface as a monitored object.
6. What the Design Side Can Do First
Reliability is not solely a manufacturing responsibility; design inputs also set the difficulty. Without touching specific numbers, three things can be settled on the design side first:
- Write the service thermal cycling condition into the technical requirements, not just the electrical specification. A factory cannot make structural recommendations for an undeclared duty cycle.
- Use staggered vias wherever density allows. When density pressure is localised, there is no reason to stack across the whole board.
- Declare which microvias are on critical paths. If specific vias failing would fail the assembly, say so up front; they can then be treated separately in sampling and verification.
The most valuable thing to supply at order release is not a tighter tolerance but intent: what environment this board must survive, for how long, and which locations cannot be allowed to fail. With that, manufacturing parameter choices have a direction.
FAQ
Q: The microvia passes electrical test. Why run thermal cycling?
A: Electrical test is a binary result proving continuity at this moment. A fully bonded via bottom and one with only a barely attached ring of copper produce identical reports. The difference appears only after temperature excursions, so cycling is needed to surface it early.
Q: Where do microvia failures most commonly occur?
A: At the via-bottom interface, where plated copper meets the target pad. A microvia is open at one end only, so Z-axis expansion is carried almost entirely by that small bond area, and initial defects propagate along it under cycling.
Q: Is more desmear safer?
A: No. Too little leaves residue in the bond interface; too much attacks the target pad and leaves uncontrolled bottom topography. It is a window-bounded operation, and sitting stably inside the window matters more than doing more of it.
Q: Which is more reliable, stacked or staggered?
A: Staggered bottoms do not superpose stress, so purely on stress they carry more margin. Stacked buys density and shorter paths. There is no universal answer; it depends on whether the board's pressure is density or cycling severity, and the call must come before routing.
Q: Does conforming plating thickness mean the via bottom is sound?
A: That inference does not hold. Thickness is a dimension; bonding is an interface condition. A section can show conforming thickness alongside a discontinuous interface line. A report giving only thickness has not answered reliability.
Q: Does a passing thermal cycling report guarantee the whole lot?
A: No. It shows the process was capable on that batch, not that every microvia conforms. Lot coverage comes from process parameter stability and sampling representativeness.