An IC substrate sits between the die and the system board. One face takes the die's bond wires or bumps; the other connects to the main board through BGA balls. Its line width, via size and warpage limits are an order of magnitude tighter than a standard PCB or HDI board, so main-board habits do not carry over.
A new package needs two decisions on the substrate before anything else:
- Interconnect: wire bond (WB) or flip chip (FC).
- Material system: glass-reinforced BT resin core, or glass-free ABF build-up film.
The interconnect sets the die-side pad structure and surface finish. The material system sets the achievable line width and the warpage behaviour. Stack-up, via structure and qualification follow from these two choices. The process boundary between HDI and substrate-like PCB is covered in SLP vs HDI: mSAP and subtractive processes and is not repeated here.
1. Interconnect first: WB vs FC
| Item | Wire bond (WB) | Flip chip (FC) |
|---|---|---|
| Die connection | Gold or copper wire from die pad to substrate bond finger | Die bumps soldered directly onto a substrate pad array |
| I/O location | Die perimeter only | Full die area |
| Critical substrate surface | Bondability of the finger plating | Bump-pad coplanarity and reflow warpage |
| Typical use | Memory, sensors, low/mid I/O packages | CPU, GPU, ASIC, high I/O packages |
When the I/O count is high and the die perimeter cannot fit the wires, FC is the only option. For low/mid I/O and cost-sensitive parts, WB is the more mature structure.
2. Then the material: BT vs ABF
| Item | BT resin | ABF build-up film |
|---|---|---|
| Construction | Glass-reinforced BT core and prepreg | Glass-free film laminated layer by layer |
| Line formation | Subtractive or mSAP | SAP (semi-additive) |
| Finest line/space (published production range) | mSAP class: 25/25 µm standard, 20/20 µm advanced | SAP: 15/15 µm standard, 10/10 µm advanced |
| Tg (representative vendor data) | approx. 190–270 °C depending on grade | approx. 155–175 °C |
| Character | Stiff and dimensionally stable; warpage easier to hold | Finest lines; film and capacity are scarce |
These figures are the representative ranges published on the IC substrate capability page. The exact grade and stack-up are confirmed during engineering review.
ABF has no glass, so laser drilling and fine lines are easier. Its stiffness comes from the core and a symmetric build-up, which makes warpage control depend more on stack-up design. BT has glass support and suits packages that need dimensional stability more than the finest lines.
3. Warpage and CTE: why package houses qualify substrates separately
Silicon expands far less than an organic substrate. During reflow the two move differently and the substrate warps. FC bumps can open or bridge, and the BGA balls can lose contact with the main board.
- FC substrates: reflow warpage is a critical item and bump-pad coplanarity is tightly held.
- WB substrates: warpage affects bonding and moulding, but coplanarity demands are lower than for FC.
The published room-temperature warpage window is ≤0.7% of the diagonal (standard) and ≤0.5% (advanced). Warpage along the reflow profile is agreed separately during engineering review.
4. Selection guide
| Condition | Usual direction |
|---|---|
| High I/O, fine bump pitch, processor-class die | FC + ABF |
| Mid I/O, memory or RF module, dimensional stability needed | FC or WB + BT |
| Low/mid I/O, cost-sensitive, mature structure | WB + BT |
| Line width below 15 µm required | ABF (SAP) |
These are common tendencies, not rules. Layer count, build-up stages and die size can change the answer.
5. Inputs to freeze before quote and review
- Substrate type: FC-BGA, FC-CSP, WB-BGA, SLP and so on.
- Total layer count and build-up: core layers, build-up stages per side, coreless or not. SKPCB IC substrates run 4–14 layers standard and 16–64 layers on request after review.
- Finest line/space class: decides mSAP or SAP.
- Substrate outline: affects panel utilisation and warpage.
- Bump or bond-finger pitch: published bump pitch is 80 µm standard, 40 µm advanced.
- Surface finish: ENIG and OSP standard; ENEPIG, electrolytic Ni/Au and solder bump / SOP pads advanced. WB fingers normally need a bondable gold layer.
- Warpage specification: measurement method and limits at room temperature and under reflow.
The first four items drive the quotation. The rest is completed at DFM review.
How SKPCB delivers
SKPCB owns the stack-up and impedance design, DFM review, qualification management and delivery of IC substrates. Fabrication takes place on dedicated substrate lines and at specialist substrate fabs, not on a general printed-board line. Details are on the IC substrate page. If the main board is HDI, see HDI PCB. To get a quote, send the inputs above through Request a quote.
FAQ
Q: Is BT or ABF better?
A: Neither in general. ABF gives finer lines for high-I/O flip chip. BT is stiffer and more dimensionally stable, which suits memory, RF modules and wire-bond packages.
Q: Can a wire-bond substrate use ABF?
A: Yes, but it is uncommon. WB line widths are usually met by BT, so ABF's fine-line capability goes unused at a higher cost.
Q: Why are substrate warpage limits tighter than PCB limits?
A: The CTE gap between silicon and an organic substrate is large, and warpage during reflow directly causes open or bridged bumps. FC substrates are the most sensitive.
Q: What is the minimum information for a quote?
A: Substrate type, total layer count with the build-up structure, the finest line/space class and the substrate outline. Other parameters are confirmed at DFM review.
Q: Does SKPCB fabricate IC substrates in-house?
A: SKPCB owns the engineering, review, qualification management and delivery. Fabrication is done on dedicated substrate lines and at specialist substrate fabs.