A substrate-like PCB (SLP) sits between an IC substrate and an HDI board. Its routing density approaches substrate class, yet it still ships as a finished board. What separates it from HDI is not layer count or build-up level. It is how the copper pattern is formed.
For the HDI process sequence, see HDI PCB manufacturing process. For ABF/BT materials and package types, see IC substrates and SLP. This article covers only the subtractive/mSAP boundary and the design inputs that change when you cross it.
Parameter comparison
| Item | HDI (subtractive) | SLP (mSAP) | ABF substrate (SAP) |
|---|---|---|---|
| Line / space | 2/2 mil | 25/25 µm standard, 20/20 µm advanced | 15/15 µm standard, 10/10 µm advanced |
| Laser via | 0.075 mm | φ60 µm standard, φ40 µm advanced | φ60 µm standard, φ40 µm advanced |
| Interconnect | 1+N+1 to 5+N+5 | Any-layer (ELIC) | Build-up / coreless |
| Layers or thickness | 4–20 layers | 0.6–1.0 mm finished | 4–14 layers (standard) |
| Delivered as | Finished board | Finished board | Package substrate |
Values are from SKPCB's published HDI PCB and IC substrate pages. SLP and substrate work is engineered by SKPCB and built on dedicated substrate lines; advanced windows are confirmed per stack-up with the substrate line.
Subtractive: start with copper, etch it away
The subtractive process starts from full copper foil. Dry film protects the circuit and the rest of the copper is etched off. Etchant attacks sideways as well as down, so the trace cross-section is a trapezoid, wider at the base than at the top, and undercut grows with copper thickness.
At wide line widths the undercut is a small share of the trace. Below roughly 50 µm, etch factor and side-wall undercut start to dominate the tolerance budget. Compensation becomes the same order of magnitude as the line itself, and both width uniformity and impedance stop converging. Imaging matters too, see LDI vs film fine-line limits, but sharper imaging does not remove undercut.
mSAP: define the channel, then plate copper into it
mSAP (modified semi-additive process) runs in the opposite order:
- A very thin seed copper layer is formed on the dielectric.
- Dry film is exposed and developed to open channels where traces will be.
- Pattern plating fills the channels with copper.
- After stripping, a flash etch removes the seed layer outside the traces.
The side walls are defined by the dry film, not by etching, so the cross-section is close to rectangular. The flash etch only has to remove a thin seed layer, which erodes far less width than subtractive undercut. That is why SLP can produce 25/25 µm at volume on a finished-board format.
Why cross-section shape affects impedance
Impedance is modelled on the conductor cross-section. A trapezoid's top and bottom widths shift with copper thickness and etch lot, and effective width varies along a single net. A near-rectangular section has similar top and bottom widths; remaining variation comes mainly from dry-film resolution and plating uniformity, so impedance consistency improves sharply.
For the designer, this means stack-up calculations after the move to SLP should use an mSAP cross-section model, not HDI etch compensation. Impedance targets and test method should be reconfirmed with engineering.
Via structure: from build-up levels to any-layer
HDI organises blind vias by build-up level, from 1+N+1 to 5+N+5, with laser vias typically φ75–100 µm. SLP is based on any-layer interconnect: every layer can connect through a laser via, down to φ60 µm (φ40 µm advanced), and stacked vias rely on via-fill plating.
Smaller vias mean smaller capture pads and tighter registration margin. For stacked versus staggered choices, see HDI via stacking, staggered and any-layer limits; for plating aspect ratio, see laser-drilled microvia plating and aspect ratio.
When SLP is not needed
- The finest routing fits inside the HDI window (2/2 mil).
- The bottleneck is layer count or board thickness, not per-layer density.
- Required thickness is outside the typical SLP finished range of 0.6–1.0 mm.
- Density is local and can be solved with an extra build-up level or a revised BGA fan-out.
SLP solves per-layer routing density and board area. If that is not the constraint, switching adds material and qualification work without a return.
Inputs to freeze when moving from HDI to SLP
| Input | Typical HDI practice | What to state for SLP |
|---|---|---|
| Line / space | Given with etch compensation | Finished target, and which layers run mSAP |
| Cross-section model | Trapezoid | Near-rectangular, stack-up calculated for mSAP |
| Impedance | HDI model | Recalculated, test method confirmed |
| Interconnect | Build-up level | Any-layer, or local mSAP layers |
| Via and pad | 0.075 mm laser via | φ60 µm or φ40 µm with matching pad size |
| Finished thickness | Per stack-up | Within 0.6–1.0 mm or not |
| Material | FR-4/BT/ABF | Dielectric confirmed for mSAP with the substrate line |
| Verification | Standard HDI acceptance | Microsection, impedance and electrical test agreed separately |
Once the stack-up and critical nets are settled, submit them through the quote page. Engineering will confirm in the EQ which layers run mSAP and whether the advanced window needs review.
Summary
The HDI/SLP boundary is how the line is formed. Subtractive relies on etching, and below about 50 µm undercut dominates tolerance. mSAP defines the channel in dry film and plates the trace, giving a near-rectangular section. Moving to SLP means restating line width, cross-section model, impedance, via size and thickness for the new process rather than carrying HDI compensation habits forward.
FAQ
Q: What is the fundamental difference between SLP and HDI?
A: How the trace is formed. HDI etches copper foil subtractively; SLP plates traces into dry-film channels with mSAP.
Q: Why does subtractive etching struggle below about 50 µm?
A: Undercut becomes the same order of magnitude as the line width, so etch factor dominates width tolerance and impedance consistency.
Q: How fine can SLP go?
A: SKPCB's published SLP/mSAP window is 25/25 µm standard and 20/20 µm advanced; the advanced window is confirmed per build with the substrate line.
Q: What thickness range does SLP cover?
A: The published SLP key spec is 0.6–1.0 mm finished thickness.
Q: Can only some layers be switched to mSAP?
A: That depends on the specific stack-up and is reviewed per design. The data should state the forming process and target line width for each layer.
Q: Does SKPCB run its own SLP line?
A: SLP and IC substrates are engineered by SKPCB and built on dedicated substrate lines. DFM review, stack-up and qualification are handled by SKPCB engineering.