HDI Laser Via Registration and Capture Pad Allowance: Manufacturing Limits

1. What "the laser via missed" actually means

The most common line in an HDI prototype failure report is "the laser via is off." That sentence has no actionable meaning on the manufacturing side, because it collapses two completely different failures into one.

Laser drilling in HDI does something unusual: it drills through the dielectric that was just laminated in this buildup cycle, and the feature it must hit was built in the previous cycle and has already been through a lamination press. That feature is the capture pad (the target pad at the via bottom; German-language documents often call it the Zielpad).

So there are two coordinate systems in play:

1. The laser system's coordinate frame, fitted from the fiducial marks it reads on the panel surface;
2. The capture pad's actual coordinate frame, set by the previous cycle's imaging and etching plus the dimensional movement the dielectric and copper went through during lamination.

There is always residual between the two. It cannot be driven to zero, because the second frame was frozen the moment lamination finished. The laser system can only approximate it; it cannot change it.

The real question in HDI registration is therefore not "how large is the residual" but who absorbs it. The answer is the annular ring that remains after you subtract the via diameter from the capture pad diameter. That ring is the entire error budget. Once it is consumed, the via lands outside the pad and the bottom metallization has nothing to connect to.

This frames everything that follows: registration accuracy is a budget shared between design and manufacturing, not an equipment spec you can request from a fab.

> One clarification up front: mechanical hole position accuracy is a different quantity. SKPCB's published hole position accuracy of ±0.05 mm (normal) applies to mechanical drilling. It cannot be reused to describe a laser via's ability to hit a capture pad, because the governing factor there is the pad's post-lamination position, not the drill's positioning repeatability.

2. Where the residual comes from

Walk the process in order and HDI layer-to-layer misregistration has four independent sources. They are not the same thing and they are not handled the same way.

(1) Dimensional reproduction in the imaging layer

After exposure, development and etching, the traces and pads on an inner layer or a previous buildup level sit slightly off from the design data. This is an imaging-process reproduction issue. Its signature is systematic and directionally consistent, and a whole-layer scaling compensation usually absorbs most of it.

(2) Dimensional movement during lamination

Lamination heats and presses the dielectric and copper to cure. The base material shrinks or expands during this, and X and Y are usually unequal. This is the hardest of the four to predict, because it depends on material grade, copper distribution, layer sequence, and how many press cycles the core has already seen.

Its key property: movement can only be measured after lamination, and laser drilling happens after lamination. That means the fab has a genuine opportunity to re-measure the actual panel after pressing and adjust this cycle's imaging and laser data accordingly. That opportunity is the subject of the next section.

(3) Fiducial reading and fit residual

The laser system builds its frame from fiducial marks on the panel. But there are only a limited number of fiducials, and panel distortion is not a rigid-body translation — it can include rotation, unequal scaling in X and Y, and genuinely non-uniform local movement.

Fitting a non-uniformly distorted panel from a handful of points necessarily leaves residual, and that residual is not evenly distributed in space: small near the fiducials, largest at whichever region sits furthest from them (typically panel center or panel corners, depending on fiducial layout).

This is where engineers commonly misjudge the problem. They assume registration error is a constant across the panel. It is a field that varies with position, which means on one panel some vias land well and others sit marginal, and that is normal behavior rather than a sporadic defect.

(4) Reference drift with buildup level

Each added level means another full round of lamination → laser drill → hole metallization → plating → imaging → etch. All three residual categories above regenerate in every round.

One distinction needs stating clearly: residual does not simply add up linearly. If the fab re-measures the panel and re-fits fiducials at every level, each level's fit residual is rebuilt rather than inherited — this is one of the more consequential process design choices in HDI manufacturing. But even with per-level rebuilding, the reference chain itself is getting longer: the level-3 capture pad was made at level 2, and the level-2 position already carries level-1 residual.

SKPCB's HDI capability is up to 5 levels (5+N+5), production-qualified rather than development-grade. The more levels, the longer that reference chain, and the more the capture pad allowance strategy needs to be specified per level instead of as one panel-wide value.

3. Three inputs design has to specify

The conclusion should be clear by now: a fab can reduce residual, not eliminate it. The inputs that decide whether the job works sit on the design side. If the following three are absent from the data package, the fab applies default rules, and the default may not match your intent.

Input 1: top pad and capture pad need separate callouts

This is the most frequently skipped item. Many designs give both pads of a laser via the same diameter, but they carry entirely different risk:

• The top pad sits on this cycle's imaging layer. It and the laser via are produced in the same round, with no lamination in between. Its registration risk is comparatively low, and its diameter is driven mainly by this layer's routing density and the outer-layer minimum trace capability.
• The capture pad sits one level down, separated from the laser via by a complete lamination cycle. It is the source of the annular ring that absorbs all layer-to-layer residual.

Giving both the same diameter forces an either/or: either the capture pad is undersized and short on allowance, or the top pad is oversized and eats this layer's routing channels. In dense regions that tradeoff is a real area conflict.

What to do: list the two pads on separate lines in the stackup drawing or fabrication notes, and state explicitly that the capture pad must not be reduced along with the top pad.

Input 2: is local scaling compensation authorized

As noted, post-lamination movement can be measured and compensated after pressing. Two approaches exist:

• Global scaling: scale the whole layer by one factor. Simple to implement, but only absorbs proportional distortion.
• Zoned compensation: apply different compensation per panel region, which can absorb non-uniform distortion. More capable, but it makes the actual imaged dimensions slightly different at different panel locations.

The second approach matters for designs with tight trace width or impedance control. SKPCB's trace width tolerance is ±20%, and impedance control tolerance is ±10% standard with ±5% as a conditional capability. If your design runs close to either boundary, whether zoned compensation is permitted has to be stated up front rather than left to the fab.

What to do: write either "scaling compensation permitted as process requires" or "compensation scheme requires engineering confirmation" in the fabrication notes. Either is workable, but one of them must be present.

Input 3: does allowance scale with buildup level

The reference chain lengthens with level count, which means a high-level capture pad faces a wider residual distribution than a low-level one.

But sizing every level's capture pad to the highest level's requirement is usually impractical — it wastes substantial routing area in the lower levels.

What to do: if your stackup has more than two levels, specify capture pad diameters per level in the stackup drawing, or at minimum state that high-level capture pads may be enlarged per level during engineering review and that such enlargement is not treated as a design change. That one sentence avoids a round of back-and-forth during prototyping.

4. Global offset vs local offset: how to tell them apart

This is the most actionable part of this guide. When a cross-section or X-ray shows a laser via off-center on its capture pad, do not immediately file it as a registration tolerance failure. Classify it first, because the two failure types differ in cause, ownership and remedy.

Method: sample several comparable vias at different panel positions and compare the direction and magnitude of the offset.

The practical value of this table is that it tells you who to talk to and what to change:

• Global offset means one setting is wrong. It looks worst (the entire panel is off) but it is actually the easiest to fix — find the wrong setting and you are done.
• Local offset looks mild (only some vias are marginal), but it is a capability boundary problem, not a setup error. Rerunning with the same fiducial layout and the same allowance will not improve the result.
• A single-via anomaly misclassified as a registration problem sends engineering off to change fiducials and compensation while the real cause sits elsewhere. That is the most time-wasting misdiagnosis of the three.

A common trap: using "yield is acceptable" to conclude registration is fine. The signature of local offset is precisely a yield that is non-zero but unstable, because whether a marginal via fails depends on which side of the distribution that lot's dimensional movement landed on. Yield variability is a symptom of local offset, not evidence against it.

5. What to verify, and with what

HDI layer-to-layer registration cannot be judged from finished-board appearance, because the connection at the via bottom is internal and invisible from the surface. The available methods:

• Cross-section (microsection analysis): destructive, and the only direct evidence of the laser via bottom's position relative to the capture pad.
• X-ray: non-destructive, suitable for the in-plane position of via relative to pad.
• Electrical test: SKPCB runs 100% electrical test (flying probe or fixture) on all orders. Electrical test finds connections that are already open; it does not find vias whose allowance is fully consumed but not yet open.
• AOI: inspects this cycle's imaging and via-opening morphology; it cannot directly judge bottom-side registration to the previous level.

One limitation deserves to be stated plainly: passing electrical test does not mean there is registration allowance left. A via that has drifted to the pad edge with only a sliver of overlap still reads as continuous. Those vias are risk points under subsequent thermal cycling. Registration capability therefore has to be judged from positional evidence in a cross-section or X-ray, not from an electrical test report alone.

SKPCB accepts to IPC-6012 Class II and Class III with 10+ quality gates. But an acceptance class defines the criteria; it does not decide for you whether the allowance is sufficient. The allowance is what you specified at design time.

6. Position-related inputs to include with the order

Condensing the above into something directly executable. If these are missing, the fab applies defaults:

1. Per-level stackup callouts: which levels have laser vias, and the start and stop layer of each.
2. Top pad and capture pad diameters on separate lines, not merged into one value.
3. Minimum acceptable capture pad diameter (not just the nominal) — this determines whether the fab has room to adjust.
4. Scaling compensation authorization: permitted / requires confirmation / not permitted. Pick one, and write it.
5. Level-dependent allowance strategy: whether high-level capture pads may be enlarged per level.
6. Fiducial definition: where the data origin sits, whether fiducials scale with the panel, whether the area around fiducials may be modified.
7. Declaration of tightly controlled features: which nets carry strict impedance or trace width requirements (this governs whether zoned compensation is available).
8. Verification requirements: whether positional evidence from cross-section or X-ray is required, and if so, which sample locations (include panel center and panel corners — these are where local offset shows up first).
9. Level count and via diameter combination: minimum laser via capability is 0.1 mm (standard) / 0.075 mm (advanced); whether a given combination is producible must be assessed together with the stackup.

Item 8 is worth underlining: if you only sample at the panel edge, the locations where local offset is worst are exactly the ones you miss. Choosing sample locations is itself part of the registration verification plan.

Related pages

• HDI PCB Capability — buildup levels, laser vias and stackup capability
• Manufacturing Tolerances — full published tolerances for hole size, hole position, trace width and impedance
• Manufacturing Capabilities — layer count, thickness, trace width and material range
• HDI Buildup Levels and Sequential Lamination — the cost of each added level as a full manufacturing round
• Laser-Drilled Microvia Aspect Ratio and Plating — how the via is formed and whether the wall can be plated
• Multilayer Lamination Registration Control — press registration and drawing callouts for conventional multilayer

FAQ

Q1: Is the laser system's positioning accuracy the same as laser via registration accuracy?

No. Positioning accuracy describes the machine's repeatability within its own coordinate frame, while the capture pad a laser via must hit lives in a different frame — one set by the previous level's imaging plus lamination movement. The laser can only approximate that frame via the panel fiducials. The residual between the two frames is the bulk of real registration error, and machine repeatability is usually not the bottleneck.

Q2: Can I just specify a layer-to-layer registration tolerance number?

You can ask, but understand what it means. Real layer-to-layer registration is a distribution that varies with panel position, not a constant. A single-value requirement forces the fab to satisfy the worst-case location, typically at the cost of enlarged capture pads or reduced routing density. A more effective approach is to state the minimum acceptable capture pad diameter, making the allowance explicit, and let the fab arrange its compensation strategy within its own capability.

Q3: Does registration error add linearly with buildup level?

Not necessarily. If the panel is re-measured and fiducials re-fitted at each level, each level's fit residual is rebuilt rather than inherited. But the reference chain itself lengthens: the level-N capture pad was produced at level N-1, and its position already carries the residual from preceding levels. So level count genuinely matters, but through chain length rather than simple summation of residuals.

Q4: Which is harder to deal with, global offset or local offset?

Local offset. Global offset is a wrong setting somewhere; find and correct it and one fix covers the whole lot. Local offset is a capability boundary set jointly by fiducial layout and panel distortion behavior. Rerunning with the same fiducial layout and allowance will not improve it; the fiducial layout, the compensation strategy, or the capture pad allowance has to change.

Q5: Does a fully passing electrical test mean registration is fine?

That inference does not hold. Electrical test finds connections that are already open. A laser via that has drifted to the capture pad edge with only a small overlap still reads as continuous, yet its allowance is gone and it is a risk point under later thermal cycling. Judging registration capability needs the positional evidence that a cross-section or X-ray provides.

Q6: Is enlarging the capture pad always safer?

Safer for registration, yes, but it consumes routing area on the level below. In a dense design, enlarging capture pads can leave that layer unroutable or force an added layer count. So it is a tradeoff between area and allowance, and it should be assessed per level and per region rather than applied as a panel-wide increase.