Writing "1 oz outer copper" does not answer the question
The most common data gap in HDI enquiries is not a missing file. It is a copper thickness given as a single number. A stack-up table saying "outer 1 oz, inner 0.5 oz" looks complete, yet engineering review still has to come back with three questions: is that base foil or finished copper after plating? What minimum wall copper do you need in the microvias? And which trace width tier should the fine-line areas be etched to?
The reason is structural. Outer copper on an HDI board is not a static property; it is the outcome of a plating step, and that step has to satisfy two requirements that pull against each other. Microvia walls need enough copper for interconnect reliability, and thicker wall copper means thicker surface copper. Thicker surface copper in turn limits the finest trace you can etch reliably. When one drawing asks for 2 mil traces and heavy via copper, both demands land on the same process.
So this article does not explain what HDI is — the process sequence is covered in HDI PCB manufacturing process. It covers one thing: how to specify the build-up level and the three copper quantities so the package clears review on the first pass.
Three copper numbers, not one
Base copper foil. The foil thickness on the laminate or core before pressing. This is the purchasing and stack-up input, and the starting point for etch compensation.
Finished copper. Total surface copper after electroless copper and electroplating. It equals base foil plus plated copper, and you do not specify it directly — it is derived from the via copper you ask for.
Microvia wall copper. Copper on the microvia barrel wall. Of the three, this is the one tied directly to reliability acceptance; the barrel wall thickness criteria in IPC-6012 and IPC-A-600 apply here.
The correct drawing practice is to state explicitly which figure is base foil and which is finished copper, and give via wall copper as a minimum. A lone "1 oz" forces a review question, and that round trip costs a day.
One sentence captures the relationship: you specify the via copper minimum, engineering works backwards through plating distribution to the required plated copper, surface finished copper follows from that, and your minimum trace capability is then locked by that finished copper. The order is one-directional. You cannot fix finished copper first and then check whether via copper happens to land in range.
Build-up level follows routing, then gets checked against the capability tier
Build-up levels are written 1+N+1, 2+N+2, up to 5+N+5: the numbers either side of the plus sign are the sequential build-up layers on each face, and N is the conventional multilayer core in the middle. The level should not be chosen on a "higher is better" basis. It should follow fan-out depth: how many layers a BGA pin has to travel inward before it can escape.
The deployed HDI PCB product page states 4–20 layers, build-ups from 1+N+1 to 5+N+5, layer-to-layer registration ±25 μm, and base materials FR-4/BT/ABF. The capabilities page adds the tier split: 1+N+1 through 5+N+5 are all available in Standard, Advanced and R&D, while Any Layer interconnection is offered only in Advanced and R&D.
That distinction matters early. If routing needs free interconnection between arbitrary layers, the project sits at Advanced or above from day one, which also means outer trace width, laser via diameter and back-drill diameter all follow the Advanced tier values. Conversely, if 1+N+1 plus conventional through-holes gets your BGA out, there is no reason to push the whole board up a tier. HDI requirements beyond 20 layers are a conditional case and must be confirmed in engineering review.
Outer copper and minimum trace width: a mutually limiting pair
In the three tiers on the capabilities page, minimum outer trace/space is 4/4 mil Standard, 3/3 mil Advanced, 2/2 mil R&D; maximum outer and inner copper is 3 oz Standard, 12 oz Advanced, >12 oz R&D. The overall copper range is 0.5 oz to >12 oz.
Those two rows cannot be read independently. More copper means more copper to etch away, which means more pronounced side etch and line-width loss, which raises the finest trace you can hold. Asking for the heaviest copper and the finest lines on the same layer puts two extremes into one process step, and that generally does not work. The practical HDI situation is the opposite: outer layers carry fine lines (the HDI product page gives 2/2 mil, with 3/3 mil fine-line features), so outer copper has to stay on the thin side. Current-carrying requirements belong on inner layers or dedicated power planes, not on a thickened outer layer.
Where fine lines and heavy copper genuinely have to coexist, the engineering options are zoned processing or a revised layer allocation. Feasibility must be confirmed in engineering review rather than settled by writing both extremes on the drawing.
Microvias, wall copper and aspect ratio
Laser drilling goes to 0.075 mm minimum (capabilities: 0.1 mm Standard, 0.075 mm Advanced and R&D); the HDI product page separately states microvia diameter ≥0.1 mm as the product-level figure. Minimum hole size is 0.075 mm, hole tolerance ±0.05 mm, position accuracy ±0.025 mm, maximum aspect ratio 10:1.
The difficulty of plating a hole does not track absolute diameter. It tracks aspect ratio — depth over diameter. The higher the ratio, the harder solution exchange becomes, and the harder it is to build copper at mid-barrel to the same thickness as at the entry. 10:1 is the through-hole capability ceiling. A microvia on its own usually sits far below that, which is exactly why microvias plate more evenly than long through-holes, but stacked microvias add effective depth, and wall copper uniformity risk rises noticeably with multiple stacked levels.
Build-up selection and via copper requirements are therefore two views of the same decision. Want more build-up levels, accept tighter wall copper uniformity control. Want to relax via copper requirements, consider staggered microvias instead of stacked. The process-side treatment of that trade-off is in HDI PCB manufacturing process.
Layer-to-layer registration at ±25 μm is the other hard constraint. A microvia has to land on the target pad below it, so pad size must leave margin for that registration tolerance. Undersize the pad and the via can miss effective connection area even with perfectly acceptable wall copper.
Inner copper and dielectric thickness jointly set impedance
Impedance is not a property of a trace in isolation. It is set by trace width, trace thickness (copper), dielectric thickness to the reference plane, and dielectric constant, together. Which means changing copper thickness changes impedance. Many designers treat copper purely as a current-carrying parameter and then find every impedance calculation needs redoing.
Deployed figures: impedance control PCB gives 25–120 Ω single-ended, 85–100 Ω differential, ±5% tolerance (±10% standard), dielectric thickness control ±10%, TDR testing, DC–40 GHz. The capabilities page states the same ±5% (±10% standard) for impedance control.
Note that dielectric thickness control is ±10% while the impedance requirement may be ±5%. The dielectric's own tolerance is wider than the impedance tolerance, which tells you impedance is not achieved by holding the dielectric alone — it is achieved by trace width and copper thickness compensating in coordination on the manufacturing side. This is why impedance boards must arrive with a stack-up and target impedances rather than trace widths only: the fab needs room to adjust line width to absorb dielectric variation. Available material and copper combinations are listed in the materials library.
The practical conclusion: if you specify ±5% impedance, do not also lock both trace width and copper thickness as immovable values, or there is no compensation margin left.
How base material choice feeds back into copper
The HDI product page lists FR-4, BT and ABF. Base material does not set copper thickness directly, but it influences copper decisions along two paths: the available clad foil and core thickness combinations differ, and the laser drilling and lamination process windows differ, which in turn affects achievable build-up levels and via copper uniformity.
BT and ABF appear more often in higher-density build-ups with thinner dielectrics, which usually pairs with thinner base foil and tighter via copper control. Viable material and copper combinations must be confirmed per project; this site does not publish a cross-material conversion table. Surface finish effects on pad solderability and fine-line protection are covered in surface finish, and the tolerance framework in manufacturing tolerances.
What the drawing package should contain
An HDI design input set that clears review on the first pass should include, for the copper-related portion:
- Stack-up table: base foil thickness per layer, dielectric material and nominal thickness, layer numbering.
- Finished copper requirement: stated separately for outer and inner layers, with "finished" or "base foil" made explicit.
- Minimum via wall copper: given separately for microvias and through-holes, with the applicable acceptance standard and class noted (IPC-6012 / IPC-A-600).
- Build-up definition: the level, such as 1+N+1 or 2+N+2, and whether microvias are stacked or staggered.
- Impedance table: net name, target impedance, tolerance (±5% or ±10%), reference plane.
- Acceptance class: IPC-A-600 Class 2 or Class 3.
- Items deliberately left to engineering review: layer counts above 20, Any Layer requirements, fine-line-plus-heavy-copper combinations, and wall copper requirements on multi-level stacked microvias. Mark these "to be confirmed in engineering review" instead of assuming a value.
Copper and stack-up freeze together. For the pre-release checklist see the multilayer PCB stackup guide and copper thickness options and design rules. Once the package is settled, submit it through the quote request.
FAQ
Q1: What happens if the drawing only says "1 oz outer copper"?
Review will ask whether that is base foil or finished copper. The two imply different actual surface copper, different etch compensation and different minimum trace capability. Prefer a form such as "0.5 oz base foil, finished copper ≥1 oz".
Q2: Can via wall copper simply be specified as "as thick as possible"?
Not advisable. Raising via copper pushes up surface finished copper, which restricts minimum trace capability, and it increases uniformity risk on multi-level stacked microvias. Specify the minimum your acceptance class requires rather than an arbitrary excess.
Q3: Can outer layers be 2/2 mil and 12 oz at the same time?
2/2 mil is an R&D tier value and 12 oz is the Advanced-and-above maximum copper, but combining both extremes on one layer requires engineering review confirmation. The conventional approach is fine lines on the outer layer with current carried on inner or dedicated power layers.
Q4: Are more build-up levels always better?
No. Level count should follow BGA fan-out depth. Higher levels bring tighter via copper uniformity and registration demands. 1+N+1 through 5+N+5 are available across all three tiers, but Any Layer is offered only in Advanced and R&D.
Q5: If copper thickness changes, does impedance need recalculating?
Yes. Copper thickness is one of the four determinants of impedance. With a ±5% impedance requirement and ±10% dielectric thickness control, the fab absorbs variation through trace width compensation, so any copper change has to go back through the impedance calculation.
Q6: What is the maximum HDI layer count?
The HDI product page states 4–20 layers; the capabilities page gives overall layer capability of 2–64 (40 Standard, 64 Advanced and R&D). Requirements beyond the HDI product page range are conditional and subject to engineering review confirmation.