The most common thermal fix in a layout review is "pour more copper." It works early, then stops working — and most projects do not know where that point is. So the copper keeps growing, the via count keeps growing, and the structural problem only surfaces at bring-up, when the fix is no longer a routing revision but a stack-up change.
This article answers one question: where the return on copper area decays past the point of being worth it, and what to switch to once you are past it. No thermal theory tour, no thermal resistance or temperature-rise numbers — those have to come from your own conditions and measurements. What you get is a decision line anchored to published manufacturing windows: which variables are already at the boundary, which still have headroom, and which structures are available once the headroom is gone.
1. Three variables that get treated as one
"Improve the thermals" routinely means three different things at once. Separating them is what makes "do we still have headroom?" an answerable question.
Copper area is two-dimensional. It sets how far heat spreads laterally away from the component pad. Adding area spreads the same heat over more board, relying on that copper's own lateral conduction before it exchanges into air and into the board body.
Copper weight is that copper's cross-section. For the same width of copper, thicker means more cross-sectional area for lateral conduction. The published window is 0.5oz → >12oz, tiered as Standard 3oz, Advanced 12oz, R&D >12oz, inner and outer layers on the same window — see Capabilities.
Thermal via arrays are the z axis. They are the only structure that moves heat from the component side of the board to the opposite side, or into inner copper planes. Their window is defined by hole size and aspect ratio: mechanical drill min 0.15mm (0.2mm at Standard), laser drill min 0.075mm, PTH max aspect ratio 10:1, with resin plug or copper paste fill available as hole treatments.
None of the three substitutes for another. That is the source of every conclusion below. Insufficient area cannot be recovered by going thicker — thickness raises conduction cross-section within the same copper, it does not extend coverage. An insufficient z-axis path cannot be recovered by pouring more copper — the heat is still stranded on the component side while you add copper on the other one. And the z-axis ceiling is not set by design intent; it is locked by board thickness and aspect ratio together.
2. Copper area: where the return decays
There is a structural reason copper area saturates: heat attenuates as it travels outward across the plane, so copper further out participates less. The effective copper area is therefore not the area you drew, but the ring heat can still reach. Copper beyond that ring is close to decoration, thermally speaking.
Three things you can check directly in the layout to know whether area is exhausted:
First, is the plane continuous? A large pour cut by signal routing forces the heat path to detour. In review, display the thermal plane alone and look for an unbroken path from source to outer edge. Slots, cutouts and dense via fields turn a nominally large plane into a narrow neck. The review object is the neck width, not the total area.
Second, is it only one layer? A single-sided pour uses one layer's conduction cross-section. On the same FR-4 board, bringing inner copper planes into the thermal path is usually more effective than extending outward on the outer layer — provided z-axis vias actually connect them. That is the next section.
Third, is there physical room left? Board edges, connectors, mounting holes and keep-out areas set the area ceiling. Once the region around the heat source is full and expanding means changing board outline or component placement, this path is done. Most teams then add vias — correct, but check first whether that channel is already at its window boundary.
3. Copper weight: what 0.5oz→>12oz actually buys
Going thicker does not extend coverage. It raises lateral conduction cross-section and current-carrying capacity within the same copper. So it helps when the copper immediately around the heat source is already the choke point, and does nothing when heat simply cannot reach far enough.
Thickness has manufacturing costs, all of them inside the published windows:
Minimum trace width rises with copper weight. Heavy Copper PCB publishes 6mil minimum trace width, while Capabilities lists outer-layer minimums of 4/4mil, 3/3mil and 2/2mil for Standard, Advanced and R&D. Heavy copper and fine lines are two different windows and you cannot take the extreme of both — heavy copper etching requires compensation, and etched sidewalls are never vertical. If the board also carries fine-pitch BGA or impedance-controlled routing, "thicken the whole board" generally does not hold.
The workable answer is a mixed-weight stack-up. The heavy-copper page states the construction explicitly: inner layers at 1–2oz carry signals while heavy copper layers (3oz to over 12oz) handle current, achieved through sequential lamination and resin-rich prepreg fill, with heavy copper etch compensation. This assigns "needs heavy copper" and "needs fine lines" to different layers. It is the standard approach for multilayer heavy-copper builds, not an exception.
Layer count and board thickness windows narrow at the same time. The heavy-copper page publishes 1–16 layers, 0.8–6.0mm board thickness, FR-4 TG170/TG180, impedance ±10%, whereas the site-wide Capabilities window is 2–64 layers, 0.2–6.0mm, impedance ±5% (±10% standard). Heavy copper drops the layer ceiling from 64 to 16, raises the minimum board thickness from 0.2mm to 0.8mm, and relaxes impedance control from ±5% to ±10%. So "add copper weight" is not a local change — it rewrites your layer, thickness and impedance budgets simultaneously. If any one of those three is already against its boundary, this path is closed.
4. Thermal via arrays: the z axis, and why it sets the ceiling
Component heat enters its own pad first. If that heat has no path through the board thickness, it can only crawl laterally within the top copper layer — and every bit of copper you poured on the bottom layer is doing nothing. A thermal via array is the only structure that connects top-side heat into inner and bottom copper.
Its ceiling is locked by three manufacturing parameters, all on Capabilities:
- Hole size: mechanical drill min 0.15mm (0.2mm at Standard), laser drill min 0.075mm.
- Aspect ratio: PTH max 10:1. A hard ceiling, defined as board thickness over hole diameter.
- Hole treatment: resin plug ✓, copper paste fill ✓.
That aspect ratio line decides something most people never calculate: change board thickness and your minimum drillable hole changes with it. At 10:1, a 1.6mm board allows 0.16mm minimum, 3.2mm allows 0.32mm, 6.0mm allows 0.60mm. Thicker board, coarser holes; coarser holes, fewer of them in the same area. So "add layers to bring inner planes in" and "use a dense fine-via field to conduct heat down" physically compete — the same constraint set visible from the multilayer lamination side, seen from a thermal angle.
Three practical points:
- For a thermal pad array, count how many fit before choosing hole size. The device center pad is fixed, pitch has to satisfy manufacturing and mask windows, so array count follows from pad area divided by pitch. It is not a free variable.
- Fill or no fill affects assembly and z-axis continuity. Unfilled thermal pads wick solder during placement, making pad void rate uncontrollable. Resin plug and copper paste fill are published treatment options and should be specified in the data package rather than left for the fab to guess.
- Count the tolerances. Hole tolerance ±0.05mm, position accuracy ±0.025mm, backdrill control ±0.05mm (see Capabilities and Manufacturing Tolerance). In a dense array these consume annular ring and spacing margin. Lay out to the post-tolerance worst case, not to nominal.
5. Four tests for when copper has run out
Meet any one of these and the copper area / copper weight path is exhausted. What follows should be a structural switch, not more copper.
Test 1 — Available copper around the source is continuous and full, and the neck is no longer the constraint. An unbroken path exists from source to board edge, neck width is no longer the narrowest link, and there is no remaining area to expand into. New copper now lands where heat does not reach.
Test 2 — The z-axis channel is at its window boundary. The via array under the thermal pad is full while still meeting annular ring and spacing tolerances, hole size is at the minimum your current board thickness allows under 10:1, and resin plug or copper paste fill is already applied. Once the z axis is maxed, no amount of copper on either side can accept more heat.
Test 3 — Outer copper weight is at its tier ceiling. Outer copper has reached the ceiling of your project's tier — 3oz (Standard), 12oz (Advanced), >12oz (R&D) — or headroom exists but fine-pitch and impedance-controlled structures on the board make whole-board thickening unworkable and a mixed-weight stack-up cannot separate them.
Test 4 — Layer, thickness or impedance budget has no headroom. You want to add layers to bring in more inner copper, but board thickness is near the 6.0mm ceiling (or the 16-layer ceiling under a heavy-copper construction), or thickening the board would push minimum hole size coarser under 10:1 and break the via array you already laid out, or the impedance window was designed to ±5% and cannot accept the ±10% that comes with heavy copper.
Use these in order, not as a score: check 1 (area left?), then 2 (z axis left?), then 3 and 4 (copper weight and layer/thickness left?). All four at the ceiling is the structural switch point.
6. Where to go past the switch point
Three paths, different manufacturable windows, all published on the site.
6.1 Heavy copper FR-4
From Heavy Copper PCB: copper 3oz → >12oz, 1–16 layers, 0.8–6.0mm board thickness, 6mil minimum trace width, FR-4 TG170/TG180, impedance ±10%, HASL/ENIG/OSP finishes.
Fits when heat and high current are the same problem — power conversion, inverters, welding equipment, motor drives, UPS — and you still need multilayer routing. The mixed-weight stack-up lets you keep signal layers on the same board. The cost is simultaneous tightening of trace width, layer ceiling, minimum thickness and impedance accuracy.
6.2 Metal core (aluminum / copper base)
From Metal Core PCB: aluminum or copper base, thermal conductivity 1.0–8.0 W/m·K, aluminum base thickness 0.8–3.0mm, copper 1oz–10oz, HASL/ENIG/OSP finishes, board size up to 1200×600mm. Listed applications include LED lighting, automotive headlights, power modules, motor drives, audio amplifiers and solar equipment.
Fits when the heat source is concentrated, heat needs to go straight into a metal body and usually onward to an external heatsink, and routing complexity is low. The page lists "single/double sided" among product features — meaning choosing metal core generally means giving up multilayer routing freedom. That is the first trade-off to confirm during selection, not a detail. The dielectric layer's own thermal-versus-dielectric-strength trade-off has its own article: Aluminum PCB insulation layer trade-offs; for the overall metal-core structure see Aluminum & Metal-Core PCB Thermal Management.
6.3 Ceramic
Only when the metal-core conductivity window is still insufficient, or operating temperature and environment exceed what organic substrates cover, do you enter ceramic (Al₂O₃ / AlN). Substrate and process selection there is a separate decision set, out of scope here.
Order of selection: first ask whether heat and current are the same problem (yes → heavy copper), then whether routing complexity can be reduced (yes → metal core), and only then whether temperature and conductivity exceed organic substrates (yes → ceramic). Picking the substrate first almost guarantees rework on routing or cost. For which manufacturing parameter caps each of the three structural paths, see PCB thermal path structures and manufacturing constraints.
7. The substrate's own temperature ceiling
Copper area, copper weight and via arrays all address moving heat out. There is a separate wall: whether the substrate can live at that temperature long term. That wall is not set by thermal structure. It is set by Tg and Td.
The published Materials Library window is wide: on the FR-4 side, from Ventec VT-42 (Tg 140°C / Td 310°C) through Isola Itera MT40 and Astra MT77 (Tg 200°C / Td 360°C) to Panasonic Megtron 7 (Tg 200°C / Td 400°C); on the polyimide side, Arlon 85N (Tg 250°C / Td 407°C) and Isola P95/P25 (Tg 260°C / Td 416°C), listed for temperature cycling. The standard substrate for heavy copper builds is FR-4 TG170/TG180 per the heavy-copper page.
The point is that Tg is unrelated to thermal design — it is a material prerequisite. If operating temperature or cycling amplitude is already near the Tg of your chosen grade, no amount of copper area fixes it: change the grade first, then discuss thermal structure. Conversely, jumping to polyimide "to be safe" brings cost and process changes, so choose against actual temperature-cycling requirements rather than instinct. Material grade, stack-up and acceptance windows are confirmed in project documents; neither this page nor the materials library replaces that confirmation.
8. Thermal fields to declare explicitly in the DFM data package
Leave these out and the fab applies defaults — and the default may not be what you want. Spell each out on submission:
- Which planes are thermal planes: their layer, the heat source they connect to, and whether later routing changes may cut them.
- Via array spec under thermal pads: hole size, pitch, count, and whether the fab may adjust for manufacturability.
- Hole treatment: resin plug, copper paste fill, or unfilled, plus mask opening approach. A wrong default directly affects assembly void rate.
- Copper weight, per layer: declare outer and inner separately; list every layer for a mixed-weight stack-up rather than writing a single "copper weight."
- Which governs, board thickness or hole size: state whether thickness is a hard constraint or may yield to hole size. This decides what gets changed first in review.
- Material grade or a Tg/Td floor: at minimum give the temperature requirement, not just "FR-4."
- Priority between impedance and thermal structure: if they conflict, say which one can give.
- Surface finish: it affects thermal pad flatness and assembly. HASL/ENIG/OSP are listed on the relevant product pages; choose against assembly requirements.
Engineering feasibility and quotation are confirmed after data and process requirements are reviewed. Getting these eight right removes a full clarification round trip. Projects ready for review can submit through the quote entry.
FAQ
Q: At what point does adding copper area stop working?
A: When available copper around the source is continuous and full with the neck no longer the constraint (Test 1), and the z-axis via array is at the boundary set by hole size and the 10:1 aspect ratio (Test 2). New copper then lands where heat does not actually reach and the return approaches zero. Actual temperature rise and thermal resistance must come from your own conditions and measurements.
Q: Copper weight or copper area — which do I add first?
A: Identify the choke point. If heat is already stalling in the copper immediately around the source, thickness helps. If heat cannot reach far enough, area helps — or bringing inner planes in via thermal vias. They address different problems. Note that thickening also tightens trace width (6mil minimum for heavy copper), layer count (1–16), minimum thickness (0.8mm) and impedance accuracy (±10%), all of which need to be budgeted together.
Q: Does a thicker board dissipate heat better?
A: That does not follow. Under a 10:1 aspect ratio, a thicker board forces a coarser minimum hole — 0.16mm at 1.6mm thickness, 0.60mm at 6.0mm. Coarser holes mean fewer of them in the same pad area, so the z-axis channel can end up narrower. Board thickness should follow stack-up and structural need, not serve as a thermal measure.
Q: Do thermal vias under a pad have to be filled?
A: Fill is a process option you declare in the data package, not a default. Resin plug and copper paste fill are both published options. Unfilled thermal pads carry a solder wicking risk during placement, which makes pad void rate harder to control. The specific choice should be confirmed during project review against assembly requirements and acceptance criteria.
Q: When do I have to move to metal core instead of optimizing further on FR-4?
A: When all four tests are at the ceiling and routing complexity can be reduced. The published metal-core window is 1.0–8.0 W/m·K conductivity, 0.8–3.0mm aluminum base, 1oz–10oz copper, with single/double sided listed among product features — it generally costs you multilayer routing freedom. If routing complexity cannot be reduced but heat and high current are the same problem, look at a heavy copper FR-4 mixed-weight stack-up first.
Q: Are these capability windows universal commitments for every product?
A: No. The Capabilities page states explicitly that the listed windows are not universal commitments for every product, and that materials, stack-up, dimensions, processes and acceptance criteria are confirmed from project data. Use the windows as feasibility boundaries in engineering review; actual combinations require project-specific confirmation.