A multilayer PCB is not built from steps you can shuffle. Once an inner layer is laminated, nobody sees it again. Once a hole is drilled, its position and size are fixed. Every parameter in the design package gets consumed by one specific process step and locked there. Knowing that order tells you which inputs must be frozen before release, and which gaps will come back as engineering queries (EQs).
SKPCB builds standard multilayer boards up to 40 layers. More layers add loops to the chain, but the main sequence stays the same.
The process chain at a glance
| Stage | Main steps | Design data consumed | What gets locked | Reversible? |
|---|---|---|---|---|
| Inner layers | Material cut, imaging, etching, inner-layer AOI | Stackup, inner Gerbers, core thickness and copper weight | Inner circuitry, inner copper distribution | No, after AOI |
| Lamination | Oxide/bond treatment, layup, pressing | Layer order, prepreg types, target thickness | Dielectric thickness, layer order, base thickness | No |
| Drilling | Mechanical drilling (plus laser drilling, back-drill) | Drill file, hole table, hole types | Hole positions, drill sizes | No |
| Hole metallization | Desmear, electroless copper, panel plating | Hole copper requirement, aspect ratio | Base hole-wall copper | No |
| Outer layers | Imaging, pattern plating, etching, outer AOI | Outer Gerbers, outer copper, trace/space | Outer circuitry, final copper | No |
| Surface | Solder mask, surface finish, legend | Mask layer, openings, finish type, silkscreen | Mask openings, solderable surface | Partly reworkable |
| Finishing | Profiling, electrical test, final inspection, packing | Outline drawing, panel drawing, netlist, acceptance class | Outline, connectivity | No (outline) |
The column that matters most is the last one. From lamination onward, almost every step seals the previous result into the board for good.
Inner layers: cut, image, etch, AOI
Material cutting picks cores to match the stackup. Core thickness and copper weight are chosen here and cannot be swapped later. Imaging transfers the inner Gerbers onto the copper, and etching removes the rest. Standard inner-layer trace/space capability is 4/4 mil.
Inner-layer AOI is the last chance to see inner circuitry directly. After lamination, inner opens, shorts or nicks can only be found indirectly by electrical test, and they cannot be repaired. How that release decision works is covered in inner-layer AOI as a one-way release gate.
Lamination: bond treatment, layup, press
Bond treatment roughens the inner copper so it grips the prepreg. Layup stacks cores, prepregs and outer foil in the specified order, and the press melts and cures the resin.
Lamination locks three things: layer order, dielectric thickness and the base board thickness. Dielectric thickness sets impedance, so impedance targets belong in the stackup alongside the dielectrics. Layer-to-layer misregistration also forms here and carries forward into drilling; see multilayer lamination registration control.
Drilling and hole metallization
Drilling goes through the laminated panel according to the drill file. Blind and buried via structures add laser drilling or sequential lamination. Standard minimum mechanical drill is 0.2 mm; 0.15 mm is an advanced capability that needs engineering review.
Metallization first removes drilling smear from the hole wall, deposits electroless copper so the wall conducts, then panel-plates it thicker. The deeper and narrower the hole, the harder it is to get enough copper into the middle, which is why through-hole aspect ratio is held to 10:1. Board thickness and minimum hole size have to be read together; details in high-layer-count PCB drilling, aspect ratio and plating throw.
Outer layers: image, plate, etch
Outer imaging puts the outer Gerbers on the panel, pattern plating builds traces and hole walls up to final copper, and etching defines the circuit. Standard outer trace/space is 4/4 mil. The heavier the outer copper, the more side etch, and the wider the finest trace you can hold.
Final outer copper equals base foil plus plated copper. It is not the single number in the stackup. A drawing that only says "1 oz outer" leaves the fab asking whether that is base or finished copper. Post-plating checks are described in PCB electroplating quality inspection and release.
Solder mask, surface finish, legend
Solder mask covers traces and exposes pads. The surface finish (ENIG, HASL, OSP and others) protects bare copper and sets solderability. Legend prints reference designators and marks. This is one of the few stages where local rework is possible, but rework affects appearance and reliability and should not be treated as design margin.
Profiling, electrical test, final inspection
Profiling routes, V-scores or punches the outline, and this is where the panel layout becomes physical. SKPCB electrically tests 100% of orders against the netlist, by flying probe or fixture; see flying probe vs fixture test for how the method is chosen. After final inspection the boards ship, with QR-code traceability from raw material to finished product.
Inputs to freeze before release
- Stackup: layer order, core and prepreg thickness, copper weight per layer (stated as base or finished)
- Target board thickness and tolerance (SKPCB range 0.2–6.0 mm)
- Impedance targets, reference planes and trace widths
- Drill file and hole table: finished hole sizes and hole types (PTH/NPTH/blind/buried/back-drill)
- Inner and outer Gerbers, mask openings, surface finish type
- Outline drawing, panel requirements and datums
- Netlist and acceptance class
Missing any of these, the fab has to stop before the matching step and raise an EQ. Capability ranges are on the multilayer PCB page; once the package is complete, submit it through the quote page.
Summary
The rule of the multilayer chain is simple: after lamination, nearly every step is irreversible. Inner layers disappear after AOI, dielectrics set at the press, holes fix at drilling, copper fixes at plating. How complete the design package is decides whether the chain runs through in one pass or stops at a node waiting for answers.
FAQ
Q: Why are inner layers processed before lamination?
A: Lamination seals inner circuitry inside the board. Imaging, etching and AOI have to finish first; afterwards inner layers cannot be reworked or repaired.
Q: After which step can the design no longer change?
A: Strictly, from inner-layer etching. The steps with the biggest design impact are lamination (layer order and dielectric thickness) and drilling (hole positions and sizes).
Q: Where is impedance decided?
A: Dielectric thickness sets at lamination and trace width sets at etching. Together they define impedance, so targets should be submitted with the stackup.
Q: Is "1 oz outer copper" enough on a drawing?
A: Not on its own. Outer copper is base foil plus plating. State whether the value is base or finished copper, or the fab will raise an EQ.
Q: How many layers can SKPCB build?
A: Standard multilayer boards go up to 40 layers. Through-hole aspect ratio is 10:1 and standard minimum mechanical drill is 0.2 mm.
Q: Is every board electrically tested?
A: Yes. SKPCB tests 100% of orders against the netlist, by flying probe or fixture.