Heat leaving a device has only three structures to travel through
Once heat leaves a device package and enters the board, there are only three classes of structure it can use: holes through the board thickness (thermal via arrays), copper spread across the board plane (heavy copper and copper planes), or a different base material entirely (metal core). These are not entry, mid and premium tiers of the same idea. They are three different physical mechanisms, and each is capped by a different manufacturing parameter.
Designs that keep re-spinning for thermal reasons usually are not miscalculating. They are adding more of the same path: another ring of vias, another ounce of copper, until some manufacturing parameter hits its boundary and the board either cannot be built or cannot be built repeatably. At that point the answer is not more of the same. It is knowing which path to switch to.
This article answers one question: which specific manufacturing parameter caps each path, and what the switch criteria are. No thermal resistance figures, no temperature rise numbers. Those need project power, airflow, enclosure and ambient conditions, which belongs to a project thermal review, not to a general article. Every figure below comes from SKPCB's published capability and product specification pages.
> For aluminium PCBs as a product type, including specification ranges and typical applications, see the aluminum PCB page. Full metal core (aluminium and copper base) ranges are on the metal core PCB page. This article does not repeat product selection; it covers the manufacturing boundaries and switch criteria of the three structural paths.
Path one: thermal via arrays, squeezed by hole size, aspect ratio and mask openings
A thermal via moves heat vertically from a device pad to the opposite side or to an internal copper plane. The advantage is that base material and copper weight stay unchanged. The entire cost sits on the drilling and hole metallisation side.
Limit 1: minimum hole size and hole tolerance. The capabilities page lists a minimum hole of 0.075 mm and hole diameter tolerance of ±0.05 mm. A smaller hole carries less conductive cross-section, so you compensate with count. But a high via count raises drilling time and bit wear, and once the pad area is filled with holes, solder will wick down through them during assembly. That is the most common practical failure with thermal vias. The handling (plugging, tenting, or placing the array beside the pad instead of on it) must be confirmed during DFM review. It cannot be assumed in the design.
Limit 2: aspect ratio ≤10:1. This is a hard constraint. On a 2.0 mm board, the hole cannot go below 0.2 mm without losing plating uniformity on the barrel wall. In other words, the thicker the board, the larger the thermal via has to stay — and thick boards are exactly the case where heat has the hardest time getting out. This path narrows itself on thick boards.
Limit 3: solder mask openings and bridges. The tolerance page states that mask openings should be 0.003″ larger than the pad, standard mask bridge is 0.004″, and pad spacing under 0.010″ may require special handling. Thermal via arrays typically sit on a device thermal pad, where pads are dense and spacing tight, so the mask bridge may simply not fit between them. That is not a thermal problem; the mask process rejects the layout first.
When this path is exhausted: the array already fills the available pad area, board thickness pins the aspect ratio at 10:1, or mask cannot bridge between features. Adding more holes past that point does not improve conduction, it only adds process risk.
Path two: heavy copper and copper planes, squeezed by trace width, layer count and thickness
The second path spreads heat laterally through copper cross-section, by increasing copper weight, enlarging copper planes, or both.
Limit 1: more copper means wider minimum traces. The capabilities page spans 0.5oz to >12oz copper and a 2/2 mil minimum trace and space — but those two extremes cannot be taken together. The heavy copper PCB page pairs 3oz to >12oz copper with a 6 mil minimum trace width. Heavy copper is formed by etching, and thicker copper means more sidewall taper and less achievable fine geometry. That is a property of the process, not something better equipment removes. So heavy copper and high-density routing are mutually exclusive: buying thermal performance in copper costs routing density.
Limit 2: layer count ceiling. The capabilities page supports 2 to 64 layers overall, but the heavy copper product page lists 1 to 16 layers. Heavy copper layers need large resin fill volumes during lamination and carry more risk of uneven layer-to-layer thickness, which compresses the layer count. A design that needs both heavy copper for heat and more than sixteen layers for signals requires engineering review for feasibility; it cannot be assumed by adding the two pages' maximum values together.
Limit 3: board thickness and impedance. The heavy copper page gives 0.8 to 6.0 mm board thickness and impedance control at ±10%, while the capabilities page states impedance control to ±5% (standard ±10%). Heavy copper widens copper thickness variation, and impedance control loosens with it. When controlled impedance shares a board with heavy copper, the impedance class must be negotiated at the heavy copper figure, not at the ±5% from the capabilities page.
When this path is exhausted: added copper has pushed minimum trace width past what the design tolerates, the layer ceiling collides with routing needs, or a controlled impedance requirement conflicts with the heavy copper class. More copper makes all three worse at once.
Path three: metal core, which changes the base material and the structural freedom with it
The third path works on neither copper nor holes. It replaces FR-4 with a metal base, so heat crosses the dielectric into the metal plate and then transfers to the chassis or heatsink.
What it buys: the metal core PCB page lists 1.0 to 8.0 W/m·K thermal conductivity, aluminium or copper base, 0.8 to 3.0 mm aluminium base thickness, and 1oz to 10oz copper, with HASL/ENIG/OSP finishes and a 1200×600 mm maximum panel. The aluminum PCB page is one step narrower: 1.0 to 3.0 W/m·K, 1oz to 6oz copper, dielectric withstand ≥3000V. Against FR-4 magnitudes, this is the only one of the three paths that changes the thermal property of the base material itself.
What it gives up:
- Layer count. The aluminum PCB page states 1 to 4 layers; the metal core page is single or double sided. That is not the same window as 2 to 64 layers on the capabilities page. Choosing metal core means giving up multilayer routing.
- Panel size figures differ by type. Aluminium runs to 1500×600 mm, metal core to 1200×600 mm, and the capabilities page overall states 1250×570 mm. Three different numbers, which means panel limits move with product type and process. Confirm against the specific product type; do not take the largest of the three.
- Via freedom. In a single or double sided construction, the via types and locations available are far fewer than on a multilayer board, and many routine design techniques are simply unavailable.
When this path is right: heat has to leave the board into the chassis, the board has no remaining copper area or via real estate, and the routing itself fits within 1 to 4 layers. That last clause is the real criterion. If the circuit does not fit in four layers, metal core is not available and the answer has to come from elsewhere (splitting the board, external heatsinking, device derating), which is project-level review territory.
Switch criteria across the three paths
The limits above reduce to three decidable statements:
- Array fills the pad, or board thickness pins aspect ratio at 10:1 → the thermal via path is done; move to copper area.
- Copper weight has forced minimum trace width to 6 mil, layer count hits the 16-layer ceiling, or impedance must stay at ±5% → the heavy copper path is done; evaluate changing base material.
- Routing fits in 1 to 4 layers and heat must go to the chassis → metal core is viable; if it does not fit in four layers, this path is closed and the answer is a project-level structural change.
The reverse holds too: if routing needs more than a dozen layers, do not shortlist metal core at all. Combine thermal vias with internal copper planes inside the multilayer framework, and confirm hole and mask manufacturability during DFM review.
Four things to submit together for review
None of these decisions can be made from a thermal requirement sheet alone. Engineering review needs to see, at the same time:
- Board thickness and target layer count, because aspect ratio and the layer ceiling decide which paths are still open.
- Minimum trace and space requirements, which determine how far copper weight can go.
- Whether controlled impedance nets exist and at which tolerance class, which decides whether heavy copper and impedance can coexist.
- Whether heat must transfer to a chassis or heatsink, plus the mechanical mounting interface, which decides whether metal core is a necessary option.
With those four in hand, manufacturing can state how much margin a given path still has on your specific board. Specific windows are confirmed from project data — the capabilities page itself notes that the listed windows are not universal commitments for every product.
FAQ
Q1: How many thermal vias, and at what pitch?
That is a project parameter, not a general value. The published constraints are a 0.075 mm minimum hole, ±0.05 mm hole tolerance, aspect ratio ≤10:1, mask openings 0.003″ larger than the pad and a 0.004″ standard mask bridge. Count and pitch must be confirmed in DFM review within those boundaries, against pad size and assembly method. This page publishes no recommended value.
Q2: Going from 3oz to 6oz copper, does heat spreading improve proportionally?
Lateral copper cross-section does increase, but manufacturing tightens in step: the heavy copper class carries a 6 mil minimum trace width, a 1 to 16 layer range and a ±10% impedance class. Actual benefit has to be weighed against those three costs, and quantifying it requires a project thermal review. No numeric conclusion is given here.
Q3: Metal core runs 1.0 to 8.0 W/m·K — is higher always better?
Higher conductivity corresponds to different base material and construction combinations, and the layer and via restrictions still apply (aluminium 1 to 4 layers, metal core single or double sided). The selection basis is where the heat has to go and whether the circuit fits the available layers, not the conductivity figure alone. The applicable class is confirmed in engineering review.
Q4: Can heavy copper and metal core be combined?
The metal core page caps copper at 1oz to 10oz and the aluminum page at 1oz to 6oz, both below the 3oz to >12oz heavy copper range, and the layer structures differ. Whether such a combination is feasible must be confirmed by engineering review against project data. No general commitment is made here.
Q5: Can a controlled impedance board still use the heavy copper path?
It can be discussed, but the impedance class has to be negotiated at the heavy copper figure: the heavy copper page states ±10%, while the ±5% on the capabilities page applies to standard impedance-controlled boards. If the design requires ±5%, the heavy copper approach needs re-review.
Q6: Can the three paths be stacked?
Within a multilayer FR-4 framework, thermal vias plus internal copper planes is the routine combination. Metal core, because of its layer restrictions (1 to 4 layers, or single/double sided), is largely exclusive with multilayer thermal via schemes. How they stack must be reviewed against the specific stackup and board thickness.